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PDF EDI2CG472256V Data sheet ( Hoja de datos )
| Número de pieza | EDI2CG472256V | |
| Descripción | 8 Megabyte Sync/Sync Burst | |
| Fabricantes | White Electronic | |
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White Electronic Designs
EDI2CG472256V
ADVANCED*
8 Megabyte Sync/Sync Burst, Dual Key DIMM
FEATURES
4x256Kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
Linear and Sequential Burst Support via MODE pin
Clock Controlled Registered Module Enable (EM#)
Clock Controlled Registered Bank Enables (E1#, E2#,
E3#, E4#)
Clock Controlled Byte Write Mode Enable (BWE#)
Clock Controlled Byte Write Enables (BW1# - BW8#)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW#)
Aysnchronous Output Enable (G#)
Internally Self-timed Write
Individual Bank Sleep Mode enables (ZZ1, ZZ2, ZZ3, ZZ4)
Gold Lead Finish
3.3V +10%, - 5% Operation
Access Speed(s): TKHQV=9, 10, 12, 15ns
Common Data I/O
High Capacitance (30pf) drive, at rated Access Speed
Single Total Array Clock
Multiple Vcc and Gnd
DESCRIPTION
The EDI2CG472256VxxD2 is a Synchronous/Synchronous
Burst SRAM, 84 position Dual Key; Double High DIMM (168
contacts) Module, organized as 4x256Kx72. The Module
contains sixteen (16) Synchronous Burst Ram Devices,
packaged in the industry standard JEDEC 14mmx20mm
TQFP placed on a Multilayer FR4 Substrate. The module
architecture is defined as a Sync/Sync Burst, Flow-
Through, with support for either linear or sequential burst.
This module provides High Performance, 2-1-1-1 accesses
when used in Burst Mode, and used as a Synchronous Only
Mode, provides a high performance cost advantage over
BiCMOS aysnchronous device architectures.
Synchronous Only operations are performed via strapping
ADSC# Low, and ADSP# / ADV# High, which provides for
Ultra Fast Accesses in Read Mode while providing for
internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in relation
to an externally supplied clock, Registered Address,
Registered Global Write, Registered Enables as well as
an Asynchronous Output enable. This Module has been
defined with full flexibility, which allows individual control
of each of the eight bytes, as well as Quad Words in both
Read and Write Operations.
*This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
EDI2CG472256V
ADVANCED
SYNCHRONOUS BURST - TRUTH TABLE
Operation
Deselected Cycle, Power Down; Bank 1
Deselected Cycle, Power Down; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Write Cycle, Begin Burst; Bank 1
Write Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 1
Read Cycle, Begin Burst; Bank 2
Read Cycle, Begin Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 1
Read Cycle, Continue Burst; Bank 2
Read Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 1
Write Cycle, Continue Burst; Bank 2
Write Cycle, Continue Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 1
Read Cycle, Suspend Burst; Bank 2
Read Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 1
E1# E2# E3# E4# ADSP# ADSC# ADV# GW# G#
HX * *
X
L
X XX
XH * *
X
L
X XX
LH * *
L
X X XL
LH * *
L
X X XH
HL * *
L
X X XL
HL * *
L
X X XH
LH * *
H
L
X LX
HL * *
H
L
X LX
LH * *
H
L
X HL
LH * *
H
L
X HH
HL * *
H
L
X HL
HL * *
H
L
X HH
XH * *
X
H
L HL
XH * *
X
H
L HH
HX * *
X
H
L HL
HX * *
X
H
L HH
HH * *
X
H
L HL
HH * *
X
H
L HH
HH * *
X
H
L HL
HH * *
X
H
L HH
XH * *
H
H
L LX
HH * *
X
H
L LX
HX * *
H
H
L LX
HH * *
X
H
L LX
XH * *
H
H
H HL
XH * *
H
H
H HH
HX * *
H
H
H HL
HX * *
H
H
H HH
HH * *
X
H
H HL
HH * *
X
H
H HH
HH * *
X
H
H HL
HH * *
X
H
H HH
XH * *
H
H
H LX
Write Cycle, Suspend Burst; Bank 1
Write Cycle, Suspend Burst; Bank 2
Write Cycle, Suspend Burst; Bank 2
HH * *
X
H
H LX
HX * *
H
H
H LX
HH * *
X
H
H LX
*All Truth Table Functions Repeat for Bank 3 (E3#) and Bank 4 (E4#)
CK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
D
D
D
D
Q
High-Z
Q
High-Z
Q
High-Z
Q
High-Z
D
D
D
D
Addr. Used
None
None
External
External
External
External
External
External
External
External
External
External
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Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
5 Page 
White Electronic Designs
EDI2CG472256V
ADVANCED
PACKAGE DESCRIPTION
Package No. 406
168 Lead
Dual Key DIMM
0.157
(2x)
195
5.255 MAX.
0.350
P1
0.450
0.575
0.925
0.078 (2X)
0.250
1.450
1.700
0.125
.050 TYP.
2.150
0.195
MAX.
1.500
MAX.
0.700
0.125
(2X)
0.225
MIN.
ORDERING INFORMATION
Part Number
EDI2CG472256V9D2*
EDI2CG472256V10D2*
EDI2CG472256V12D2
EDI2CG472256V15D2
*Consult Factory for Availability
Organization
4x256Kx72
4x256Kx72
4x256Kx72
4x256Kx72
Voltage
3.3
3.3
3.3
3.3
Speed (ns)
9
10
12
15
Package
168 Gold Lead DIMM
168 Gold Lead DIMM
168 Gold Lead DIMM
168 Gold Lead DIMM
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet EDI2CG472256V.PDF ] | |
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