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PDF P89LPC9381 Data sheet ( Hoja de datos )

Número de pieza P89LPC9381
Descripción 8-bit microcontroller
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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P89LPC9381
8-bit microcontroller with accelerated two-clock 80C51 core
4 kB 3 V byte-erasable flash with 10-bit ADC
Rev. 01 — 8 September 2006
Product data sheet
1. General description
The P89LPC9381 is a single-chip microcontroller, available in low-cost packages, based
on a high performance processor architecture that executes instructions in two to four
clocks, six times the rate of standard 80C51 devices. Many system-level functions have
been incorporated into the P89LPC9381 in order to reduce component count, board
space, and system cost.
2. Features
2.1 Principal features
I 4 kB byte-erasable flash code memory organized into 1 kB sectors and 64 B pages.
Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
I 256 B RAM data memory on-chip RAM.
I 8-input multiplexed 10-bit ADC. Two analog comparators with selectable inputs and
reference source.
I Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output) and a 23-bit system timer that can also be used
as a RTC.
I Enhanced UART with fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
I High-accuracy internal RC oscillator option allows operation without external oscillator
components. The RC oscillator option is selectable and fine tunable.
I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
I 28-pin TSSOP package with 23 I/O pins minimum and up to 26 I/O pins while using
on-chip oscillator and reset options.

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P89LPC9381 pdf
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Philips Semiconductors
5. Functional diagram
P89LPC9381
8-bit microcontroller with 10-bit ADC
AD05
AD00
AD01
AD02
AD03
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
CLKOUT
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
XTAL2
XTAL1
PORT 0
PORT 3
Fig 2. P89LPC9381 functional diagram
VDD VSS
P89LPC9381
PORT 1
TXD
RXD
T0
INT0
INT1
RST
AD04
SCL
SDA
PORT 2
AD07
AD06
MOSI
MISO
SS
SPICLK
002aac461
P89LPC9381_1
Product data sheet
Rev. 01 — 8 September 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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P89LPC9381 arduino
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Table 4. P89LPC9381 Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
addr. MSB
LSB
Reset value
Hex Binary
Bit address E7 E6 E5 E4 E3 E2
E1
E0
ACC*
Accumulator
E0H
00 0000 0000
AD0CON ADC0 control register
97H ENBI0 ENADCI TMM0 EDGE0 ADCI0 ENADC0 ADCS01 ADCS00 00
0
0000 0000
AD0INS ADC0 input select
A3H ADI07 ADI06 ADI05 ADI04 ADI03 ADI02 ADI01
ADI00 00
0000 0000
AD0MODA ADC0 mode register A
C0H BNDI0 BURST0 SCC0 SCAN0
-
-
-
- 00 0000 0000
AD0MODB ADC0 mode register B
A1H CLK2 CLK1
CLK0
-
-
-
-
- 00 000x 0000
AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST
0
-
DPS 00
0000 00x0
Bit address F7 F6 F5 F4 F3 F2
F1
F0
B* B register
F0H
00 0000 0000
BRGR0[1] Baud rate generator rate BEH
low
00 0000 0000
BRGR1[1] Baud rate generator rate BFH
high
00 0000 0000
BRGCON Baud rate generator
BDH
-
-
-
-
-
- SBRGS BRGEN 00[1] xxxx xx00
control
CMP1
Comparator 1 control
register
ACH
-
-
CE1 CP1 CN1 OE1
CO1
CMF1 00[2] xx00 0000
CMP2
Comparator 2 control
register
ADH
-
-
CE2 CP2 CN2 OE2
CO2
CMF2 00[2] xx00 0000
DIVM
CPU clock divide-by-M
control
95H
00 0000 0000
DPTR
Data pointer (2 B)
DPH
Data pointer high
83H
00 0000 0000
DPL Data pointer low
82H
00 0000 0000
FMADRH Program flash address
high
E7H
00 0000 0000
FMADRL Program flash address
low
E6H
00 0000 0000

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