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PDF DP83241 Data sheet ( Hoja de datos )
| Número de pieza | DP83241 | |
| Descripción | CDD Device | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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February 1991
DP83241 CDDTM Device
(FDDI Clock Distribution Device)
General Description
The CDD device is a clock generation and distribution de-
vice intended for use in FDDI (Fiber Distributed Data Inter-
face) networks The device provides the complete set of
clocks required to convert byte wide data to serial format for
fiber medium transmission and to move byte wide data be-
tween the PLAYERTM and BMACTM devices in various sta-
tion configurations 12 5 MHz and 125 MHz differential ECL
clocks are generated for the conversion of data to serial
format and 12 5 MHz and 25 MHz TTL clocks are generated
for the byte wide data transfers
Features
Y Provides 12 5 MHz and 25 MHz TTL clocks
Y 12 5 MHz and 125 MHz ECL clocks
Y 5 phase TTL local byte clocks eliminate clock
skew problems in concentrators
Y Internal VCO requires no varactors coils or
adjustments
Y Option for use of High Q external VCO
Y 125 MHz clock generated from a 12 5 MHz crystal
Y External PLL synchronizing reference for
concentrator configurations
Y 28-pin PLCC package
Y BiCMOS processing
FIGURE 1-1 FDDI Chip Set Block Diagram
TL F 10385 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
BMACTM BSITM CDDTM CRDTM and PLAYERTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10385
RRD-B30M105 Printed in U S A
1 page  
3 0 Pin Descriptions
Symbol
Pin I O
No
Description
DVCC
EXTVCC
16
28
Digital VCC Positive power supply for all the internal circuitry intended for operation at 5V g5% relative
to GND A bypass capacitor should be placed as close as possible across the DVCC and DGND pins
External VCC Positive power supply for all the output buffers intended for operation at 5V g5% relative
to GND A bypass capacitor should be placed as close as possible across the EXTVCC and EXTGND
pins
DGND
15
Digital Ground Internal circuit power supply return
EXTGND
1
External Ground Output buffer power supply return
AGND
14
Analog Ground Substrate ground used to ensure proper device biasing and isolation
AVCC
XTL IN
18 Analog VCC Positive power supply for the critical analog circuitry intended for a5V operation g5%
relative to Ground A bypass cap should be placed as close as possible between AVCC and AGND
8 I External Crystal Oscillator Input XTL IN can also be used as a CMOS compatible reference frequency
input for the PLL This input is selected when REF SEL is at a logical LOW level The component
connections required for oscillator operation are shown in the application diagrams
XTL OUT
6
External Crystal Oscillator Output XTL OUT is not intended for use as a logic drive output pin
REF IN
5 I Reference Input TTL compatible input for use as the PLL’s phase comparator reference frequency
input when the REF SEL is at a logic HI level This input is for use in concentrator configurations where
there are multiple CDD devices at a given site requiring synchronization
FEEDBK IN 4
I Feedback Input TTL compatible input for use as the PLL’s phase comparator feedback input to close
the loop This input is intended to be driven from one of the LBCs (Local Byte Clocks) This input is
designed to provide the same frequency and within 2 ns of the same phase as REF IN when REF IN is in
active operation
REF SEL
9 I Reference Select TTL compatible input which selects either the crystal oscillator inputs XTL IN and
XTL OUT or the REF IN inputs as the reference frequency inputs for the PLL The crystal oscillator inputs
are selected when REF SEL is at a logic LOW level and the REF IN input is selected as the reference
frequency when REF SEL is at a logic HI level
FILTER
10 O Filter Low pass PLL loop filter pin A three element filter consisting of one capacitor in parallel with a
resistor and another capacitor should be connected between this pin and ground
VCO SEL
17 I VCO Select TTL compatible input used to select either the internal VCO or an external VCO through the
XVCO IN and XVCO INB pins The internal VCO is selected when the VCO SEL pin is at a logic HIGH
level and the external VCO is selected when at a logic LOW level
XVCO IN 13
XVCO INB 12
I External VCO Inputs Differential inputs for use with an external VCO These inputs are D C biased to
approximately one half VCC and can be connected to either a full differential VCO or a single-ended
VCO To use a single-ended VCO couple the signal into one of the inputs through a series low value
capacitor and bypass the other input to GND through a 0 01 mF capacitor When not in use ground one
input and let the other float
5
5 Page 
5 0 Detailed Information
5 1 EXTERNAL COMPONENTS
The Filter components are based on a 12 5 MHz Crystal and a 250 MHz VCO
All component values g10%
FIGURE 5-1 General Wiring Diagram
TL F 10385 – 6
The Filter components are based on a 12 5 MHz Crystal and an external 250 MHz VCO with a gain of 40 MRad V
All component values g10%
FIGURE 5-2 General Wiring Diagram with an External VCO
11
TL F 10385 – 7
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet DP83241.PDF ] | |
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