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PDF DP83261 Data sheet ( Hoja de datos )
| Número de pieza | DP83261 | |
| Descripción | BMAC Device | |
| Fabricantes | National Semiconductor | |
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October 1994
DP83261 BMACTM Device
(FDDI Media Access Controller)
General Description
The DP83261 BMAC device implements the Media Access
Control (MAC) protocol for operation in an FDDI token ring
The BMAC device provides a flexible interface to the
BSI-2TM device The BMAC device offers the capabilities
described in the ANSI X3T9 5 MAC Standard and several
functional enhancements allowed by the Standard
The BMAC device transmits receives repeats and strips
tokens and frames It uses a full duplex architecture that
allows diagnostic transmission and self testing for error iso-
lation The duplex architecture also allows full duplex data
service on point-to-point connections Management soft-
ware is also aided by an array of on chip statistical counters
and the ability to internally generate Claim and Beacon
frames without program intervention A multi-frame stream-
ing interface is provided to the system interface device
Features
Y Full duplex operation with through parity
Y Supports all FDDI ring scheduling classes (asynchro-
nous synchronous restricted asynchronous and
immediate)
Y Supports individual group short long and external
addressing
Y Generates Beacon Claim and Void frames without
intervention
Y Provides extensive ring and station statistics
Y Provides extensions for MAC level bridging
Y Provides separate management interface
Y Uses low power microCMOS
TL F 10387 – 1
FIGURE 1-1 FDDI Chip Set Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
BSI-2TM BMACTM PLAYERaTM CDDTM and CRDTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10387
RRD-B30M105 Printed in U S A
1 page  
2 0 Architectural Description (Continued)
2 1 RING ENGINE
The BMAC device is operated by the Ring Engine which is
comprised of four blocks Receiver Transmitter MAC Pa-
rameter RAM and Counters Timers as shown in Figure 2-2
2 1 1 Receiver
The Receiver Block accepts data from the PLAYER device
in the byte stream format (PH Indicate)
Upon receiving the data the Receiver Block performs the
following functions
Determines the beginning and ending of a Protocol Data
Unit (PDU)
Decodes the Frame Control field to determine the PDU
type (frame or token)
Compares the received Destination and Source Address-
es with the internal addresses
Processes data within the frame
Calculates and checks the Frame Check Sequence at
the end of the frame
Checks the Frame Status field
And finally the Receiver Block presents the data to the
MAC Interface along with the appropriate control signals
(MA Indicate)
2 1 2 Transmitter
The Transmitter Block inserts frames from this station into
the ring in accordance with the FDDI Timed Token MAC
protocol It also repeats frames from other stations in the
ring The Transmitter block multiplexes data from the MA
Request Interface and data from the Receiver Block During
Frame Transmission data from the Request Interface is se-
lected During Frame Repeating data from the Receiver
Block is selected
During Frame Transmission the Transmitter Block performs
the following functions
Captures a token to gain the right to transmit
Transmits one or more frames
Generates the Frame Check Sequence during transmis-
sion and appends it at the end of the frame
Generates the Frame Status field that is transmitted at
the end of the frame
Issues the token at the end of frame transmission
During Frame Repeating the Transmitter Block performs
the following functions
Repeats the received frame and modifies the Frame
Status field at the end of the frame as specified by the
standard
Whether transmitting or repeating frames the Transmitter
Block also performs the following functions
Strips the frame(s) that are transmitted by this station
Generates Idle symbols between frames
Data is presented from the Transmitter Block to the
PLAYER device in the byte stream format (PH Request)
2 1 3 MAC Parameter RAM
The MAC Parameter RAM block is a dual port RAM that
contains MAC parameters such as the station’s short and
long addresses These parameters are initiallzed via the
Control Interface Both the Receiver and Transmitter Blocks
may access the RAM
FIGURE 2-2 Ring Engine Overview Block Diagram
5
TL F 10387 – 4
5 Page 
4 0 FDDI MAC Facilities (Continued)
Frames Generated Externally
The Ring Engine transmits frames passed to it from the Sys-
tem Interface The data portion of the frame is created by
the System Interface This begins with the FC field and ends
with the last byte of the INFO field The FC field is passed
transparently to the ring The length bit in the FC field is
used to determine the length of the transmitted addresses
The data is passed as a byte stream across the MAC Re-
quest Interface as shown in Table 4-5
Before the frame is transmitted the Ring Engine inserts the
Start of Frame Sequence with at least 8 bytes of Preamble
but no more than 40 bytes of Preamble The starting delimi-
ter is transmitted as a JK symbol pair The Source Address
is normally transmitted by the Ring Engine since it uses the
Source Address to strip the frame from the ring This can be
overridden by using the Source Address transparency capa-
bility Similarly the Frame Check Sequence (4 bytes) is nor-
mally transmitted by the Ring Engine This can be overrid-
den with the FCS transparency capability With FCS trans-
parency the FCS is transmitted from the data stream The
End of Frame Sequence is always transmitted by the Ring
Engine as TR RR
Frames transmitted by the Ring Engine must have a valid
DA and SA field If the end of a frame is reached before a
valid length is transmitted the frame will be aborted and a
Void frame will be transmitted
TABLE 4-5 Frame Formats
Field
PA
SD
FC
DA
SA
INFO
Size
t8 s40
1
1
2 or 6
2 or 6
t0
MA Request
FC
DA
SA
INFO
PH Request
Idle Pairs
JK
FC
DA
MSA MLA
or SA
INFO
FCS 4 if Present
ED 1
FS 1
FCS
FCS
TR
RR
Frames Generated by the Ring Engine
The Ring Engine generates and detects several frames in
order to attain and maintain an operational ring
Void Frames
Void frames are used during normal operation The Ring
Engine generates two types of void frames regular Void
frames and My Void frames See Table 4-6
If short addressing is enabled Void frames with the short
address are transmitted otherwise Void frames with the
long address are transmitted
Void frames are transmitted in order to reset the Valid
Transmission timers (TVX) in other stations in order to elimi-
nate an unnecessary entry to the Claim state Stations are
not required to copy Void frames Void frames are transmit-
ted by the Ring Engine in two situations
1 While holding a token when no data is ready to be trans-
mitted
2 After a frame transmission is aborted
My Void frames are transmitted by the Ring Engine in
three situations
1 After a request to measure the Ring Latency has been
made when the next early token is captured
2 After this station wins the Claim Process before the token
is issued
3 After a frame has been transmitted with the STRIP option
before the token for that service opportunity is issued
Void frames are also detected by the Ring Engine A Void
frame with a Source Address other than MSA or MLA is
considered an Other Void frame
Claim Frames
Claim frames are generated continuously with minimum pre-
amble while the Ring Engine is in the Transmit Claim state
The format of Claim frames generated by the Ring Engine is
shown in Table 4-7 When long addressing is enabled
frames with the long address are transmitted otherwise
frames with the short address are transmitted
The Ring Engine detects reception of valid Claim frames A
comparison is performed between the (first) four bytes of
the received INFO field and TREQ in order to distinguish
Higher Claim Lower Claim and My Claim Details are
given in Appendix A
TABLE 4-6 Void Frames
Type
Enable
Size
SFS
FC DA
SA FCS EFS
Void
Void
ESA
Short PA SD 00 Null MSA FCS TRRR
Not ESA Long PA SD 40 Null MLA FCS TRRR
My Void
ESA
Short PA SD 00 MSA MSA FCS TRRR
My Void Not ESA Long PA SD 40 MLA MLA FCS TRRR
TABLE 4-7 Claim Frames
Type
Enable
Size
SFS
FC DA
SA
INFO
FCS
EFS
My Claim Not ELA Short PA SD 83 MSA MSA TREQ FCS TRRR
My Claim ELA Long PA SD C3 MLA MLA TREQ FCS TRRR
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DP83261.PDF ] | |
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