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ADP3196 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP3196
Beschreibung 6-Bit Programmable 2- to 4-Phase Synchronous Buck Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
ADP3196 Datasheet, Funktion
www.DataSheet4U.com
6-Bit Programmable 2- to 4-Phase
Synchronous Buck Controller
ADP3196
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to 1 MHz
per phase
±10 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to external
high power drivers
Enhanced PWM flex mode for excellent load transient
performance
Active current balancing between all output phases
Built-in power-good/crowbar blanking supports on-the-fly
VID code changes
Digitally programmable 0.3750 V to 1.55 V output
Programmable short-circuit protection with programmable
latch-off delay
APPLICATIONS
Desktop PC power supplies for next generation
AMD processors
VRM modules
GENERAL DESCRIPTION
The ADP31961 is a highly efficient multiphase synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Advanced Micro Devices, Inc. (AMD) processors.
It uses an internal 6-bit DAC to read a voltage identification
(VID) code directly from the processor, which is used to set the
output voltage between 0.3750 V and 1.55 V.
This device uses a multimode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase
relationship of the output signals can be programmed to provide
2-, 3-, or 4-phase operation, allowing for the construction of up to
four complementary buck switching stages.
The ADP3196 supports a programmable slope function to
adjust the output voltage as a function of the load current so
that it is always optimally positioned for a system transient. This
can be disabled by connecting Pin LLSET to Pin CSREF.
1Protected by U.S. Patent Number 6,683,441; others patents pending.
FUNCTIONAL BLOCK DIAGRAM
VCC
31
RT RAMPADJ
12 13
GND 18
SHUNT
REGULATOR
UVLO
SHUTDOWN
800mV
EN 1
+
1.8V
CSREF
+
DAC – 250mV
+
PWRGD 2
DELAY
TTSENSE 10
VRMHOT 9
VRM_OFF 8
THERMAL
THROTTLING
CONTROL
OSCILLATOR
CURRENT
BALANCING
CIRCUIT
+
CMP
+
CMP
+
–CMP
+
CMP
SET EN
RESET
RESET
RESET
2-/3-/4-PHASE
DRIVER LOGIC
RESET
19 OD
30 PWM1
29 PWM2
28 PWM3
27 PWM4
CROWBAR
CURRENT
LIMIT
25 SW1
24 SW2
23 SW3
22 SW4
ILIMIT 11
DELAY 7
IREF 20
COMP 5
FBRTN 3
PRECISION
REFERENCE
CURRENT
MEASUREMENT
AND LIMIT
+
+
+
SOFT START
CONTROL
17 CSCOMP
15 CSREF
16 CSSUM
21 IMON
4 FB
14 LLSET
6 SS
VID DAC
34 35 36 37 38 39
VID5 VID4 VID3 VID2 VID1 VID0
ADP3196
Figure 1. Functional Block Diagram
The ADP3196 also provides accurate and reliable short-circuit
protection, adjustable current limiting, and a delayed power-
good output that accommodates on-the-fly output voltage
changes requested by the CPU. The ADP3196 has a built-in
shunt regulator that allows the part to be connected to the 12 V
system supply through a series resistor.
The ADP3196 is specified over the extended commercial
temperature range of 0°C to +85°C and is available in a
40-lead LFCSP.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






ADP3196 Datasheet, Funktion
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC
FBRTN
PWM3 – PWM4, RAMPADJ
SW1 – SW4
<200 ns
All Other Inputs and Outputs
Storage Temperature
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (θJA)
Lead Temperature
Soldering (10 sec)
Infrared (15 sec)
Rating
−0.3 V to +6 V
−0.3 V to +0.3 V
−0.3 V to VCC + 0.3 V
−5 V to +25 V
−10 V to +25 V
−0.3 V to VCC + 0.3 V
−65°C to +150°C
0°C to 85°C
125°C
100°C/W
300°C
260°C
ADP3196
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified all other
voltages referenced to GND.
ESD CAUTION
Rev. 0 | Page 6 of 20

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ADP3196 pdf, datenblatt
ADP3196
VOLTAGE CONTROL MODE
A high gain, high bandwidth voltage mode error amplifier is
used for the voltage mode control loop. The control input
voltage to the positive input is set via the VID logic according to
the voltages listed in Table 4.
The voltage is also offset by the droop voltage for active
positioning of the output voltage as a function of current,
commonly known as active voltage positioning. The output of
the amplifier is the COMP pin, which sets the termination
voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with
Resistor RB and is used for sensing and controlling the output
voltage at this point. A current source (equal to IREF/2) flows
through RB into the FB pin and is used for setting the no load
offset voltage from the VID voltage. The no load offset is
positive with respect to the VID DAC. The main loop
compensation is incorporated into the feedback network
between FB and COMP.
CURRENT REFERENCE
The IREF pin is used to set an internal current reference. This
reference current sets IFB, IDELAY, ISS, ILIMIT, and ITTSENSE. A resistor
to ground programs the current based on the 1.5 V output.
1.5 V
IREF =
RIREF
Typically, RIREF is set to 100 kΩ to program IREF = 15 µA. The
following currents are then equal to:
IFB = 1/2 (IREF) = 7.5 μA
IDELAY = IREF = 15 μA
ISS(STARTUP) = 1/4 (IREF) = 3.75 μA
ISS(DAC) = 5/4 (IREF) = 18.75 μA
ILIMIT = 2/3 (IREF) = 10 μA
ITTSENSE = 8 (IREF) = 120 μA
ENHANCED PWM MODE
Enhanced PWM mode is intended to improve the transient
response of the ADP3196 to a load stepup. In previous
generations of controllers, when a load stepup occurred, the
controller had to wait until the next turn on of the PWM signal
to respond to the load change. Enhanced PWM mode allows
the controller to respond immediately when a load stepup
occurs. This allows the phases to respond when the load
increase transition takes place.
DELAY TIMER
The delay times for the start-up timing sequence are set with a
capacitor from the DELAY pin to ground. In UVLO or when
EN is logic low, the DELAY pin is held at ground. After the
UVLO and EN signals are asserted, the first delay time (TD1 in
Figure 7) is initiated. A current flows out of the DELAY pin to
charge CDLY. This current is equal to IREF, which is normally
15 µA. A comparator monitors the DELAY voltage with a
threshold of 1.7 V.
The delay time is therefore set by the IREF current charging a
capacitor from 0 V to 1.7 V. This DELAY pin is used for two
delay timings (TD1 and TD3) during the start-up sequence. In
addition, DELAY is used for timing the current limit latch off as
explained in the Current Limit, Short-Circuit, and Latch-Off
Protection section.
SOFT START
The soft start ramp rates for the output voltage are set up with a
capacitor from the soft start (SS) pin to ground. During startup,
the SS pin sources a current of 3.75 μA. After startup, when a
DAC code change occurs, the SS pin sinks or sources an
18.75 μA current to control the rate at which the output voltage
can transition up or down.
During startup (after TD1 and the phase detection cycle are
complete), the SS time (TD2 in Figure 7) starts. The SS pin is
disconnected from GND and the capacitor is charged up to the
programmed DAC voltage by the SS amplifier, which has an
output current equal to one quarter IREF (normally 3.75 µA).
The voltage at the FB pin follows the ramping voltage on the
SS pin, limiting the inrush current during startup. The soft start
time depends on the value of the initial DAC voltage and CSS.
Note that the DAC code must be set before the ADP3196 is
enabled.
Once the SS voltage is within 50 mV of the programmed DAC
voltage, the power-good delay time (TD3) starts. Once TD2 has
completed, the soft start current changes to 18.75 µA. If the
programmed DAC code changes after startup, then the SS pin
sources or sinks a current of 18.75 μA to or from the SS
capacitor. This occurs until the SS voltage is within 50 mV of
the newly programmed DAC voltage.
If EN is taken low or VCC drops below UVLO, DELAY and SS are
reset to ground in preparation for another soft start cycle.
Figure 8 shows typical start-up waveforms for the ADP3196,
while Figure 9 shows a typical DAC code change waveform.
Rev. 0 | Page 12 of 20

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