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AD7747 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7747
Beschreibung 24-Bit Capacitance-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 29 Seiten
AD7747 Datasheet, Funktion
24-Bit Capacitance-to-Digital Converter
with Temperature Sensor
AD7747
FEATURES
GENERAL DESCRIPTION
Capacitance-to-digital converter
New standard in single chip solutions
Interfaces to single or differential grounded sensors
Resolution down to 20 aF (that is, up to 19.5-bit ENOB)
Accuracy: 10 fF
Linearity: 0.01%
Common-mode (not changing) capacitance up to 17 pF
Full-scale (changing) capacitance range ±8 pF
Update rate: 5 Hz to 45 Hz
Simultaneous 50 Hz and 60 Hz rejection at 8.1 Hz update
Active shield for shielding sensor connection
Temperature sensor on-chip
Resolution: 0.1°C, accuracy: ±2°C
Voltage input channel
Internal clock oscillator
2-wire serial interface (I2C® compatible)
Power
2.7 V to 5.25 V single-supply operation
0.7 mA current consumption
Operating temperature: −40°C to +125°C
16-lead TSSOP package
APPLICATIONS
Automotive, industrial, and medical systems for
Pressure measurement
Position sensing
Proximity sensing
Level sensing
Flow metering
Impurity detection
The AD7747 is a high-resolution, Σ-Δ capacitance-to-digital
converter (CDC). The capacitance to be measured is connected
directly to the device inputs. The architecture features inherent
high resolution (24-bit no missing codes, up to 19.5-bit effective
resolution), high linearity (±0.01%), and high accuracy (±10 fF
factory calibrated). The AD7747 capacitance input range is
±8 pF (changing), and it can accept up to 17 pF common-mode
capacitance (not changing), which can be balanced by a program-
mable on-chip digital-to-capacitance converter (CAPDAC).
The AD7747 is designed for single-ended or differential
capacitive sensors with one plate connected to ground. For
floating (not grounded) capacitive sensors, the AD7745 or
AD7746 are recommended.
The part has an on-chip temperature sensor with a resolution of
0.1°C and accuracy of ±2°C. The on-chip voltage reference and
the on-chip clock generator eliminate the need for any external
components in capacitive sensor applications. The part has a
standard voltage input that, together with the differential reference
input, allows easy interface to an external temperature sensor,
such as an RTD, thermistor, or diode.
The AD7747 has a 2-wire, I2C-compatible serial interface. The
part can operate with a single power supply of 2.7 V to 5.25 V.
It is specified over the automotive temperature range of
−40°C to +125°C and is housed in a 16-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN(+)
TEMP
SENSOR
CLOCK
GENERATOR
AD7747
VIN(–)
CIN1(+)
CIN1(–)
SHLD
MUX
24-BIT Σ-Δ
GENERATOR
DIGITAL
FILTER
I2C
SERIAL
INTERFACE
EXCITATION
CAP DAC 1
CAP DAC 2
CONTROL LOGIC
CALIBRATION
VOLTAGE
REFERENCE
SDA
SCL
RDY
REFIN(+) REFIN(–)
Figure 1.
GND
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.






AD7747 Datasheet, Funktion
AD7747
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
SERIAL INTERFACE1, 2
SCL Frequency
SCL High Pulse Width, tHIGH
SCL Low Pulse Width, tLOW
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Hold Time (Start Condition), tHD;STA
Setup Time (Start Condition), tSU;STA
Data Setup Time, tSU;DAT
Setup Time (Stop Condition), tSU;STO
Data Hold Time, tHD;DAT (Master)
Bus-Free Time (Between Stop and Start Condition, tBUF)
Min Typ Max Unit
0 400 kHz
0.6 μs
1.3 μs
0.3 μs
0.3 μs
0.6 μs
0.6 μs
0.1 μs
0.6 μs
0 μs
1.3 μs
Test Conditions/Comments
See Figure 2
After this period, the first clock is generated
Relevant for repeated start condition
1 Sample tested during initial release to ensure compliance.
2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
SCL
tLOW
tR
SDA
tBUF
PS
tHD;STA
tHD;DAT
tF
tHIGH
tSU;DAT
tHD;STA
tSU;STA
S
Figure 2. Serial Interface Timing Diagram
tSU;STO
P
Rev. 0 | Page 5 of 28

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AD7747 pdf, datenblatt
AD7747
OUTPUT NOISE AND RESOLUTION SPECIFICATIONS
The AD7747 resolution is limited by noise. The noise
performance varies with the selected conversion time.
Table 5 shows typical noise performance and resolution for the
capacitive channel. These numbers were generated from 1000
Table 6 and Table 7 show typical noise performance and
resolution for the voltage channel. These numbers were
generated from 1000 data samples acquired in continuous
conversion mode with VIN pins shorted to ground.
data samples acquired in continuous conversion mode, at an
RMS noise represents the standard deviation and p-p noise
excitation of 16 kHz, ±VDD × 3/8, and with all CIN and SHLD
pins connected only to the evaluation board (no external
capacitors).
represents the difference between minimum and maximum
results in the data. Effective resolution is calculated from rms
noise, and p-p resolution is calculated from p-p noise.
Table 5. Typical Capacitive Input Noise and Resolution vs. Conversion Time (Bold line represents default setting)
Conversion
Time (ms)
22.0
23.9
40.0
76.0
124.0
154.0
184.0
219.3
Output Data
Rate (Hz)
45.5
41.9
25.0
13.2
8.1
6.5
5.4
4.6
−3 dB Frequency
(Hz)
43.6
39.5
21.8
10.9
6.9
5.3
4.4
4.0
RMS Noise
(aF/√Hz)
28.8
23.2
11.1
11.2
11.0
10.4
10.0
9.0
RMS
Noise (aF)
190
146
52
37
29
24
21
18
P-P
Noise (aF)
821
725
411
262
174
173
141
126
Effective Resolution
(Bits)
16.4
16.8
18.3
18.7
19.1
19.3
19.6
19.9
P-P Resolution
(Bits)
14.3
14.5
15.3
15.9
16.5
16.5
16.8
17.0
Table 6. Typical Voltage Input Noise and Resolution vs. Conversion Time, Internal Voltage Reference
Conversion
Time (ms)
20.1
32.1
62.1
122.1
Output Data
Rate (Hz)
49.8
31.2
16.1
8.2
−3 dB Frequency
(Hz)
26.4
15.9
8.0
4.0
RMS Noise
(μV)
11.4
7.1
4.0
3.0
P-P Noise
(μV)
62
42
28
20
Effective Resolution
(Bits)
17.6
18.3
19.1
19.5
P-P Resolution
(Bits)
15.2
15.7
16.3
16.8
Table 7. Typical Voltage Input Noise and Resolution vs. Conversion Time, External 2.5 V Voltage Reference
Conversion
Time (ms)
20.1
32.1
62.1
122.1
Output Data
Rate (Hz)
49.8
31.2
16.1
8.2
−3 dB Frequency
(Hz)
26.4
15.9
8.0
4.0
RMS Noise
(μV)
14.9
6.3
3.3
2.1
P-P Noise
(μV)
95
42
22
15
Effective Resolution
(Bits)
18.3
19.6
20.5
21.1
P-P Resolution
(Bits)
15.6
16.8
17.7
18.3
Rev. 0 | Page 11 of 28

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