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PDF PCA9547 Data sheet ( Hoja de datos )
| Número de pieza | PCA9547 | |
| Descripción | 8-Channel I2C Bus Multiplexer | |
| Fabricantes | NXP Semiconductors | |
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PCA9547
8-channel I2C-bus multiplexer with reset
Rev. 02 — 12 September 2006
Product data sheet
1. General description
The PCA9547 is an octal bidirectional translating multiplexer controlled by the I2C-bus.
The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only one
SCx/SDx channel can be selected at a time, determined by the contents of the
programmable control register. The device powers up with Channel 0 connected, allowing
immediate communication between the master and downstream devices on that channel.
An active LOW reset input allows the PCA9547 to recover from a situation where one of
the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the
I2C-bus state machine causing all the channels to be deselected, except Channel 0 so
that the master can regain control of the bus.
The pass gates of the multiplexers are constructed such that the VDD pin can be used to
limit the maximum high voltage which will be passed by the PCA9547. This allows the use
of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can communicate
with 5 V parts without any additional protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features
I 1-of-8 bidirectional translating multiplexer
I I2C-bus interface logic; compatible with SMBus standards
I Active LOW RESET input
I 3 address pins allowing up to 8 devices on the I2C-bus
I Channel selection via I2C-bus, one channel at a time
I Power-up with all channels deselected except Channel 0 which is connected
I Low Ron multiplexers
I Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
I No glitch on power-up
I Supports hot insertion
I Low standby current
I Operating power supply voltage range of 2.3 V to 5.5 V
I 5 V tolerant inputs
I 0 Hz to 400 kHz clock frequency
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Packages offered: SO24, TSSOP24, HVQFN24
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Philips Semiconductors
PCA9547
8-channel I2C-bus multiplexer with reset
5.2 Pin description
Table 3.
Symbol
A0
A1
RESET
SD0
SC0
SD1
SC1
SD2
SC2
SD3
SC3
VSS
SD4
SC4
SD5
SC5
SD6
SC6
SD7
SC7
A2
SCL
SDA
VDD
Pin description
Pin
SO, TSSOP HVQFN
1 22
2 23
3 24
41
52
63
74
85
96
10 7
11 8
12 9[1]
13 10
14 11
15 12
16 13
17 14
18 15
19 16
20 17
21 18
22 19
23 20
24 21
Description
address input 0
address input 1
active LOW reset input
serial data output 0
serial clock output 0
serial data output 1
serial clock output 1
serial data output 2
serial clock output 2
serial data output 3
serial clock output 3
supply ground
serial data output 4
serial clock output 4
serial data output 5
serial clock output 5
serial data output 6
serial clock output 6
serial data output 7
serial clock output 7
address input 2
serial clock line
serial data line
supply voltage
[1] HVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
PCA9547_2
Product data sheet
DataSheet4 U .com
Rev. 02 — 12 September 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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Philips Semiconductors
PCA9547
8-channel I2C-bus multiplexer with reset
7.4 Bus transactions
Data is transmitted to the PCA9547 control register using the Write mode as shown in
Figure 12.
slave address
control register
SDA S 1 1 1 0 A2 A1 A0 0 A X X X X B3 B2 B1 B0 A P
START condition
R/W acknowledge
from slave
acknowledge
from slave
STOP condition
002aaa988
Fig 12. Write control register
Data is read from PCA9547 using the Read mode as shown in Figure 13.
slave address
control register
last byte
SDA S 1 1 1 0 A2 A1 A0 1 A X X X X B3 B2 B1 B0 NA P
START condition
Fig 13. Read control register
R/W acknowledge
from slave
no acknowledge
from master
STOP condition
002aaa989
PCA9547_2
Product data sheet
DataSheet4 U .com
Rev. 02 — 12 September 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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