|
|
PDF ADSP-TS202S Data sheet ( Hoja de datos )
| Número de pieza | ADSP-TS202S | |
| Descripción | TigerSHARC Embedded Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ADSP-TS202S (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
Preliminary Technical Data
KEY FEATURES
500 MHz, 2.0 ns Instruction Cycle Rate
12M Bits of Internal—On-Chip—DRAM Memory
25×25 mm (576-Ball) Thermally Enhanced Ball Grid Array
Package
Dual Computation Blocks—Each Containing an ALU, a Multi-
plier, a Shifter, and a Register File
Dual Integer ALUs, providing Data Addressing and Pointer
Manipulation
Integrated I/O Includes 14 Channel DMA Controller, External
Port, Four Link Ports, SDRAM Controller, Programmable
Flag Pins, Two Timers, and Timer Expired Pin for System
Integration
1149.1 IEEE Compliant JTAG Test Access Port for On-Chip
Emulation
On-Chip Arbitration for Glueless Multiprocessing
TigerSHARC®
Embedded Processor
ADSP-TS202S
KEY BENEFITS
Provides High-Performance Static Superscalar DSP Opera-
tions, Optimized for Large, Demanding Multiprocessor
DSP Applications
Performs Exceptionally Well on DSP Algorithm and I/O
Benchmarks (See Benchmarks in Table 1)
Supports Low-Overhead DMA Transfers Between Internal
Memory, External Memory, Memory-Mapped Peripherals,
Link Ports, Host Processors, and Other (Multiprocessor)
DSPs
Eases DSP Programming Through Extremely Flexible Instruc-
tion Set and High-Level-Language Friendly DSP
Architecture
Enables Scalable Multiprocessing Systems With Low Commu-
nications Overhead
DATA ADDRESS GENERATION
INTEGER 32
J ALU
32 INTEGER
K ALU
PROGRAM
SEQUENCER
ADDR
FETCH
32X32
J-BUS ADDR
J-BUS DATA
32X32
BTB
K-BUS ADDR
K-BUS DATA
I-BUS ADDR
PC I-BUS DATA
TIAB
12M BITS INTERNAL MEMORY
MEMORY BLOCKS
(PAGE CACHE)
4xCROSSBAR CONNECT
32 A D A D A D A D
128
32
128
32
128
S-BUS ADDR
32
S-BUS DATA 128
X
REGISTER
FILE
32x32
128
128
DAB
DAB
128
Y
128 REGISTER
FILE
32x32
COMPUTATIONAL BLOCKS
SOC BUS
JTAG PORT
6
JTAG
EXTERNAL
PORT
HOST
32
ADDR
MULTI
PROC
64
DATA
SDRAM 8
CTRL
CTRL
C-BUS
ARB
10
CTRL
EXT DMA
REQ 4
DMA
LINK PORTS
4
IN 8
L0 4
OUT 8
4
IN 8
L1 4
OUT 8
4
IN 8
L2 4
OUT 8
4
IN 8
L3 4
OUT 8
Figure 1. Functional block diagram
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
PROGRAM SEQUENCER
The ADSP-TS202S processor’s program sequencer supports the
following:
• A fully interruptible programming model with flexible pro-
gramming in assembly and C/C++ languages; handles
hardware interrupts with high throughput and no aborted
instruction cycles
• A ten-cycle instruction pipeline—four-cycle fetch pipe and
six-cycle execution pipe—computation results available
two cycles after operands are available
• Supply of instruction fetch memory addresses; the
sequencer’s Instruction Alignment Buffer (IAB) caches up
to five fetched instruction lines waiting to execute; the pro-
gram sequencer extracts an instruction line from the IAB
and distributes it to the appropriate core component for
execution
• Management of program structures and program flow
determined according to JUMP, CALL, RTI, RTS instruc-
tions, loop structures, conditions, interrupts, and software
exceptions
• Branch prediction and a 128-entry branch target buffer
(BTB) to reduce branch delays for efficient execution of
conditional and unconditional branch instructions and
zero-overhead looping; correctly predicted branches that
are taken occur with zero overhead cycles, overcoming the
five-to-nine stage branch penalty
• Compact code without the requirement to align code in
memory; the IAB handles alignment
Interrupt Controller
The DSP supports nested and nonnested interrupts. Each inter-
rupt type has a register in the interrupt vector table. Also, each
has a bit in both the interrupt latch register and the interrupt
mask register. All interrupts are fixed as either level-sensitive or
edge-sensitive, except the IRQ3–0 hardware interrupts, which
are programmable.
The DSP distinguishes between hardware interrupts and soft-
ware exceptions, handling them differently. When a software
exception occurs, the DSP aborts all other instructions in the
instruction pipe. When a hardware interrupt occurs, the DSP
continues to execute instructions already in the instruction pipe.
Flexible Instruction Set
The 128-bit instruction line, which can contain up to four 32-bit
instructions, accommodates a variety of parallel operations for
concise programming. For example, one instruction line can
direct the DSP to conditionally execute a multiply, an add, and a
subtract in both computation blocks while it also branches to
another location in the program. Some key features of the
instruction set include:
• Algebraic assembly language syntax
• Direct support for all DSP, imaging, and video arithmetic
types
ADSP-TS202S
• Eliminates toggling DSP hardware modes because modes
are supported as options (for example, rounding, satura-
tion, and others) within instructions
• Branch prediction encoded in instruction; enables zero-
overhead loops
• Parallelism encoded in instruction line
• Conditional execution optional for all instructions
• User defined partitioning between program and data
memory
DSP MEMORY
The DSP’s internal and external memory is organized into a
unified memory map, which defines the location (address) of all
elements in the system, as shown in Figure 3.
The memory map is divided into four memory areas—host
space, external memory, multiprocessor space, and internal
memory—and each memory space, except host memory, is sub-
divided into smaller memory spaces.
The ADSP-TS202S processor internal memory has 12M bits of
on-chip DRAM memory, divided into six blocks of 2M bits
(64K words × 32 bits). Each block—M0, M2, M4, M6, M8, and
M10—can store program, data, or both, so applications can
configure memory to suit specific needs. Placing program
instructions and data in different memory blocks, however,
enables the DSP to access data while performing an instruction
fetch. Each memory segment contains a 128K bit cache to
enable single cycle accesses to internal DRAM.
The six internal memory blocks connect to the four 128-bit wide
internal buses through a crossbar connection, enabling the DSP
to perform four memory transfers in the same cycle. The DSP’s
internal bus architecture provides a total memory bandwidth of
28G bytes per second, enabling the core and I/O to access eight
32-bit data words and four 32-bit instructions each cycle. The
DSP’s flexible memory structure enables:
• DSP core and I/O accesses to different memory blocks in
the same cycle
• DSP core access to three memory blocks in parallel—one
instruction and two data accesses
• Programmable partitioning of program and data memory
• Program access of all memory as 32-, 64-, or 128-bit
words—16-bit words with the DAB
EXTERNAL PORT (OFF-CHIP
MEMORY/PERIPHERALS INTERFACE)
The ADSP-TS202S processor’s external port provides the DSP’s
interface to off-chip memory and peripherals. The 4G word
address space is included in the DSP’s unified address space.
The separate on-chip buses—four 128-bit data buses and four
32-bit address buses—are multiplexed at the SOC interface and
transferred to the external port over the SOC bus to create an
external system bus transaction. The external system bus pro-
vides a single 64-bit data bus and a single 32-bit address bus.
The external port supports data transfer rates of 1G bytes per
second over the external bus.
Rev. PrB | Page 5 of 40 | December 2003
5 Page 
Preliminary Technical Data
of the mouse, examine run-time stack and heap usage. The
Expert Linker is fully compatible with existing Linker Definition
File (LDF), allowing the developer to move between the graphi-
cal and textual environments.
Analog Devices DSP emulators use the IEEE 1149.1 JTAG Test
Access Port of the ADSP-TS202S processor to monitor and con-
trol the target board processor during emulation. The emulator
provides full speed emulation, allowing inspection and modifi-
cation of memory, registers, and processor stacks. Nonintrusive
in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the TigerSHARC processor family.
Hardware tools include TigerSHARC processor PC plug-in
cards. Third party software tools include DSP libraries, real-
time operating systems, and block diagram design tools.
DESIGNING AN EMULATOR-COMPATIBLE DSP
BOARD (TARGET)
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. The emulator uses
the TAP to access the internal features of the DSP, allowing the
developer to load code, set breakpoints, observe variables,
observe memory, and examine registers. The DSP must be
halted to send data and commands, but once an operation has
been completed by the emulator, the DSP system is set running
at full speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68”. This document is updated regularly
to keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-
TS202S processor’s architecture and functionality. For detailed
information on the ADSP-TS202S processor’s core architecture
and instruction set, see the ADSP-TS201 TigerSHARC Processor
Hardware Reference and the ADSP-TS201 TigerSHARC Proces-
sor Programming Reference. For detailed information on the
development tools for this processor, see the VisualDSP++
User’s Guide for TigerSHARC Processors.
ADSP-TS202S
Rev. PrB | Page 11 of 40 | December 2003
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADSP-TS202S.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ADSP-TS202S | TigerSHARC Embedded Processor | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |