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AD7021 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7021
Beschreibung High Performance Narrowband ISM Transceiver IC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 44 Seiten
AD7021 Datasheet, Funktion
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Preliminary Technical Data
High Performance Narrowband
ISM Transceiver IC
ADF7021
FEATURES
Low power, low IF transceiver
Frequency bands
80 MHz to 650 MHz
862 MHz to 940 MHz
Modulation schemes
2FSK, 3FSK, 4FSK
Spectral shaping
Gaussian and raised-cosine filtering
Data rates supported
0.05 kbps to 25 kbps
2.3 V to 3.6 V power supply
Programmable output power
−16 dBm to +13 dBm in 63 steps
Automatic PA ramp control
Receiver sensitivity
−125 dBm at 1 kbps, 2 FSK
On-chip VCO and fractional-N PLL
RSET
On-chip 7-bit ADC and temperature sensor
Fully automatic frequency control loop (AFC)
Digital RSSI
Integrated Tx/Rx switch
Leakage current <1 μA in power-down mode
APPLICATIONS
Narrow-band standards
ETSI EN 300-220, FCC Part 90, FCC Part 15, FCC Part 95,
ARIB STD-T67
Low cost, wireless data transfer
Remote control/security systems
Wireless metering
Private mobile radio
Wireless medical telemetry service (WMTS)
Keyless entry
Home automation
Process and building control
Pagers
FUNCTIONAL BLOCK DIAGRAM
CE CREG(1:4)
MUXOUT
RLNA
POLARIZATION
TEMP
SENSOR
MUX
7-BIT ADC
LDO(1:4)
TEST MUX
RFIN
RFINB
LNA
GAIN
IF FILTER
RSSI/
OFFSET
CORRECTION
2FSK
3FSK
4FSK
DEMODULATOR
CLOCK
AND DATA
RECOVERY
Tx/Rx
CONTROL
PA RAMP
RFOUT
DIVIDERS/
MUXING
MUX
VCO
AGC
CONTROL
AFC
CONTROL
SERIAL
PORT
DIV P
N/N + 1
Σ-Δ
MODULATOR
2FSK
3FSK
4FSK
MOD CONTROL
CP PFD
DIV R
RING OSC
CLK
DIV
GAUSSIAN/
RAISED COSINE
FILTER
3FSK
ENCODING
L1 L2 VCOIN CPOUT
OSC1 OSC2
Figure 1.
CLKOUT
DATA CLK | TxDATA
DATA I/O | RxDATA
SWD
SLE
SDATA
SREAD
SCLK
Rev. PrI
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
DataSheet4 U .com
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






AD7021 Datasheet, Funktion
www.DataSheet4U.com
ADF7021
Parameter
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
Control Clock Input
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
CLKOUT Rise/Fall
CLKOUT Load
TEMPERATURE RANGE (TA)
POWER SUPPLIES
Voltage Supply
VDD
Transmit Current Consumption
0 dBm
10 dBm
0 dBm
10 dBm
Receive Current Consumption
Low Current Mode
High Sensitivity Mode
Power-Down Mode
Low Power Sleep Mode
Min Typ
0.7 × V DD
DVDD − 0.4
−40
2.3
12.7
21
19.3
28
20
22
0.1
Max Unit
0.2 ×
VDD
±1
10
50
V
V
μA
pF
MHz
V
0.4 V
5 ns
10 pF
+85 °C
3.6 V
mA
mA
mA
mA
mA
mA
1 μA
1 For definition of frequency deviation, see the Register 2—Transmit Modulation Register section.
2 Measured as maximum unmodulated power. Output power varies with both supply and temperature.
3 For matching details, see the LNA/PA Matching section.
4 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks.
5 See Table 8 for a description of different receiver modes.
6 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.
Preliminary Technical Data
Test Conditions
IOH = 500 μA
IOL = 500 μA
All VDD pins must be tied together
VDD = 3.0 V, PA is matched into 50 Ω
FRF = 460 MHz
FRF = 460 MHz
FRF = 868 MHz
FRF = 868 MHz
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Rev. PrI | Page 6 of 44

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AD7021 pdf, datenblatt
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ADF7021
FREQUENCY SYNTHESIZER
REFERENCE INPUT
The on-board crystal oscillator circuitry (see Figure 7) can use
an inexpensive quartz crystal as the PLL reference. The oscil-
lator circuit is enabled by setting R1_DB12 high. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected by using the automatic frequency
control feature or by adjusting the fractional-N value (see the N
Counter section). A single-ended reference (TCXO, CXO) can
also be used. The CMOS levels should be applied to OSC2 with
R1_DB12 set low.
OSC1
OSC2
CP2 CP1
Figure 7. Oscillator Circuit on the ADF7021
Two parallel resonant capacitors are required for oscillation at
the correct frequency. Their values are dependent upon the
crystal specification. They should be chosen to make sure that
the series value of capacitance added to the PCB track
capacitance adds up to the load capacitance of the crystal,
usually 18 pF to 20 pF. Track capacitance values vary from 2 pF
to 5 pF, depending on board layout. When possible, choose
capacitors that have a very low temperature coefficient to
ensure stable frequency operation over all conditions.
Programmable Crystal Bias Current
Bias current in the oscillator circuit can be configured between
20 μA and 35 μA by writing to Bits R1_DB[13:14].
CLKOUT Divider and Buffer
The CLKOUT circuit takes the reference clock signal from the
oscillator section, shown in Figure 7, and supplies a divided-
down 50:50 mark-space signal to the CLKOUT pin. An even
divide from 2 to 30 is available. This divide number is set in
R1_DB[7:10]. On power-up, the CLKOUT defaults to divide-by-8.
DVDD
CLKOUT
ENABLE BIT
OSC1
DIVIDER
1 TO 15
÷2
CLKOUT
Figure 8. CLKOUT Stage
To disable CLKOUT, set the divide number to 0. The output
buffer can drive up to a 20 pF load with a 10% rise time at
4.8 MHz. Faster edges can result in some spurious feedthrough
to the output. A small series resistor (50 Ω) can be used to slow
the clock edges to reduce these spurs at FCLK.
Preliminary Technical Data
R Counter
The 3-bit R counter divides the reference input frequency by an
integer from 1 to 7. The divided-down signal is presented as the
reference clock to the phase frequency detector (PFD). The
divide ratio is set in Register 1. Maximizing the PFD frequency
reduces the N value. This reduces the noise multiplied at a rate
of 20 log(N) to the output and reduces occurrences of spurious
components. Register 1 defaults to R = 1 on power-up:
PFD [Hz] = XTAL/R
Loop Filter
The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. A typical loop filter design is shown in Figure 9.
CHARGE
PUMP OUT
VCO
Figure 9. Typical Loop Filter Configuration
The loop should be designed so that the loop bandwidth (LBW)
is approximately three times the data rate. Widening the LBW
excessively reduces the time spent jumping between
frequencies, but can cause insufficient spurious attenuation.
Narrow-loop bandwidths can result in the loop taking long
periods of time to attain lock. Careful design of the loop filter is
critical to obtain accurate modulation.
When using the Gaussian or raised cosine data filtering options,
it is recommended to use a LBW of 2.0 to 2.5 times the data rate
to ensure that sufficient samples of the input data are taken
while filtering system noise. The free design tool ADIsimPLL
can be used to design loop filters for the ADF7021.
N Counter
The feedback divider in the ADF7021 PLL consists of an 8-bit
integer counter and a 15-bit Σ-Δ fractional-N divider. The
integer counter is the standard pulse-swallow type common in
PLLs. This sets the minimum integer divide value to 23. The
fractional divide value gives very fine resolution at the output,
where the output frequency of the PLL is calculated as
FOUT
=
XTAL
R
×
⎜⎜⎝⎛
Integer
_
N
+
Fractional N
215
⎟⎟⎠⎞
When VCO divide-by-2 (see the Voltage Controlled Oscillator
(VCO) section) is selected, this formula becomes:
FOUT
=
XTAL
R
×
0.5 ×
⎜⎛
Integer_N
+
Fractional N
215
⎟⎞
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