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| Número de pieza | AN211A | |
| Descripción | FIFELD EFFECT TRANSISTORS | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR APPLICATION NOTE
Order this document
by AN211A/D
NOTE: The theory in this application note is still applicable,
but some of the products referenced may be discontinued.
Field Effect Transistors in Theory
and Practice
AN211A
INTRODUCTION
There are two types of field-effect transistors, the Junction
Field-Effect Transistor (JFET) and the “Metal-Oxide
Semiconductor” Field-Effect Transistor (MOSFET), or
Insulated-Gate Field-Effect Transistor (IGFET). The
principles on which these devices operate (current controlled
by an electric field) are very similar — the primary difference
being in the methods by which the control element is made.
This difference, however, results in a considerable difference
in device characteristics and necessitates variances in circuit
design, which are discussed in this note.
DRAIN
DRAIN
GATE
GATE
SOURCE
SOURCE
NĆCHANNEL JFET
PĆCHANNEL JFET
JUNCTION FIELD-EFFECT TRANSISTOR (JFET)
In its simplest form the junction field-effect transistor starts
with nothing more than a bar of doped silicon that behaves
as a resistor (Figure 1a). By convention, the terminal into
which current is injected is called the source terminal, since,
as far as the FET is concerned, current originates from this
terminal. The other terminal is called the drain terminal.
Current flow between source and drain is related to the
drain-source voltage by the resistance of the intervening
material. In Figure 1b, p-type regions have been diffused into
the n-type substrate of Figure 1a leaving an n-type channel
between the source and drain. (A complementary p-type
device is made by reversing all of the material types.) These
p-type regions will be used to control the current flow
between the source and the drain and are thus called gate
regions.
As with any p-n junction, a depletion region surrounds
the p-n junctions when the junctions are reverse biased
(Figure 1c). As the reverse voltage is increased, the
depletion regions spread into the channel until they meet,
creating an almost infinite resistance between the source and
the drain.
If an external voltage is applied between source and drain
(Figure 1d) with zero gate voltage, drain current flow in the
channel sets up a reverse bias along the surface of the gate,
parallel to the channel. As the drain-source voltage
increases, the depletion regions again spread into the
channel because of the voltage drop in the channel which
reverse biases the junctions. As VDS is increased, the
depletion regions grow until they meet, whereby any further
increase in voltage is counterbalanced by an increase in the
depletion region toward the drain. There is an effective
increase in channel resistance that prevents any further
increase in drain current. The drain-source voltage that
causes this current limiting condition is called the “pinchoff”
voltage (Vp). A further increase in drain-source voltage
produces only a slight increase in drain current.
The variation in drain current (ID) with drain-source
voltage (VDS) at zero gate-source voltage (VGS) is shown
in Figure 2a. In the low-current region, the drain current is
linearly related to VDS. As ID increases, the “channel” begins
to deplete and the slope of the ID curve decreases. When
the VDS is equal to Vp, ID “saturates” and stays relatively
constant until drain-to-gate avalanche, VBR(DSS) is reached.
If a reverse voltage is applied to the gates, channel pinch-off
occurs at a lower ID level (Figure 2b) because the depletion
region spread caused by the reverse-biased gates adds to
that produced by VDS. Thus reducing the maximum current
for any value of VDS.
È ÈÈSOURCE
N
DRAIN
ÈÈ ÈÈÈÈ ÈÇÇÈ(a)
ÈÈÇÇÇÇÈÈGATE 1
SOURCE
GATE 1
P
N
P
DRAIN
ÈÈÈÇÇÇÇÇÇÈÈÈÇÇÇSOURCE
(-) DEPLETION ZONES
P
N
DRAIN
P
GATE 2
(b)
(-) GATE 2
(c)
ÈÈÈÇÇÇÈÈÈÇÇÇÇÇÇÈÈÈSOURCE
GATE 1
P
(+)
ID
P
DRAIN
ID
GATE 2
(d)
Figure 1. Development of Junction
Field-Effect Transistors
+VDS
VP LOCUS
ID VGS = 0
IP
ID VGS = 0
VGS = - 1 V
VGS = - 2 V
VP
VDS
V(BR)DSS
VDS
(a) (b)
Figure 2. Drain Current Characteristics
REV 0
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AN211A
source is always higher than that for the triode-connected
case where both gates are tied together.
Reach-through voltage is another specification uniquely
applicable to tetrode-connected devices. This defines the
amount of difference voltage that may be applied to the two
gates before the depletion region of one spreads into the
junction of the other — causing an increase in gate current
to some small specified value. Obviously, reach-through is
an undesirable condition since it causes a decrease in input
resistance as a result of an increased gate current, and large
amounts of reach-through current can destroy the FET.
Gate Leakage Current
Of interest to circuit designers is the input resistance of
an active component. For FETs, this characteristic is
specified in the form of IGSS — the reverse-bias
gate-to-source current with the drain shorted to the source
(Figure 11). As might be expected, because the leakage
current across a reverse-biased p-n junction (in the case of
a JFET) and across a capacitor (in the case of a MOSFET)
is very small, the input resistance is extremely high. At a
temperature of 25°C, the JFET input resistance is hundreds
of megohms while that of a MOSFET is even greater. For
junction devices, however, input resistance may decrease
by several orders of magnitude as temperature is raised to
150°C. Such devices, therefore, have gate-leakage current
specified at two temperatures. Insulated-gate FETs are not
drastically affected by temperature, and their input resistance
remains extremely high even at elevated temperatures.
Gate leakage current may also be specified as IGDO
(leakage between gate and drain with the source open), or
as IGSO (leakage between gate and source with the drain
open). These usually result in lower values of leakage current
and do not represent worst-case conditions. The IGSS
specification, therefore, is usually preferred by the user.
Voltage Breakdown
A variety of specifications can be used to indicate the
maximum voltage that may be applied to various elements
of a FET. Among those in common use are the following:
V(BR)GSS =
V(BR)DGO =
V(BR)DSX =
Gate-to-source breakdown voltage
Drain-to-gate breakdown voltage
Drain-to-source breakdown voltage
(normally used only for MOSFETs)
In addition, there may be ratings and specifications
indicating the maximum voltages that may be applied
between the individual gates and the drain and source (for
tetrode connected devices). Obviously, not all of these
specifications are found on every data sheet since some of
them provide the same information in somewhat different
form. By understanding the various breakdown mechanisms,
however, the reader should be able to interpret the intent
of each specification and rating. For example:
In junction FETs, the maximum voltage that may be
applied between any two terminals is the lowest voltage that
will lead to breakdown or avalanche of the gate junction. To
measure V(BR)GSS (Figure 12a), an increasingly higher
reverse voltage is applied between the gate and the source.
Junction breakdown is indicated by an increase in gate
current (beyond IGSS) which signals the beginning of
avalanche.
Some reflection will reveal that for junction FETs, the
V(BR)DGO specification really provides the same information
as V(BR)GSS. For this measurement, an increasing voltage
is applied between drain and gate. When this applied voltage
becomes high enough, the drain-gate junction will go into
avalanche, indicated either by a significant increase in drain
current or by an increase in gate current (beyond IDGO). For
both V(BR)DGO and V(BR)GSS specifications, breakdown
should normally occur at the same voltage value.
From Figure 2 it is seen that avalanche occurs at a lower
value of VDS when the gate is reverse biased than for the
zero-bias condition. This is caused by the fact that the
reverse-bias gate voltage adds to the drain voltage, thereby
increasing the effective voltage across the junction. The
maximum amount of drain-source voltage that may be
applied VDS(max) is, therefore, equal to V(BR)DGO minus
VGS, which indicates avalanche with reverse bias gate
voltage applied.
For MOSFETs, the breakdown mechanism is somewhat
different. Consider, for example, the enhancement-mode
structure of Figure 5. Here, the gate is completely insulated
from the drain, source, and channel by an oxide-nitride layer.
The breakdown voltage between the gate and any of the
other elements, therefore, is dependent on the thickness and
purity of this insulating layer, and represents the voltage that
will physically puncture the layer. Consequently, the voltage
must be specified separately.
The drain-to-source breakdown is a different matter. For
enhancement mode devices, with the gate connected to the
source (the cutoff condition) and the substrate floating, there
is no effective channel between drain and source and the
applied drain-source voltage appears across two opposed
series diodes, represented by the source-to-substrate and
substrate-to-drain junctions. Drain current remains at a very
low level (picoamperes) as drain voltage is increased until
the drain voltage reaches a value that causes reverse
(avalanche) breakdown of the diodes. This particular
condition, represented by V(BR)DSS, is indicated by an
increase in ID above the IDSS level, as shown in Figure 12b.
For depletion/enhancement mode devices, the V(BR)DSS
symbol is sometimes replaced by V(BR)DSX. Note that the
principal difference between the two symbols is the
replacement of the last subscript s with the subscript x.
Whereas the s normally indicates that the gate is shorted
to the source, the x indicates that the gate is biased to cutoff
or beyond. To achieve cutoff in these devices, a depleting
bias voltage must be applied to the gate, Figure 12b.
An important static characteristic for switching FETs is the
“on” drain-source voltage VDS(on). This characteristic for the
MOSFETs is a function of VGS, and resembles the VCE(sat)
versus IB characteristics of junction transistors. The curve
for these characteristics can be used as a design guide to
determine the minimum gate voltage necessary to achieve
a specified output logic level.
Dynamic Characteristics
Unlike the static characteristics, the dynamic
characteristics of field-effect transistors apply equally to all
FETs. The conditions and presentation of the dynamic
characteristics, however, depend largely upon the intended
application. For example, the following table indicates the
dynamic characteristics needed to adequately describe a
FET for various applications.
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MFE2012
Freescale Semiconductor, Inc.
AN211A
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AN211A.PDF ] | |
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