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GTL2008 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer GTL2008
Beschreibung (GTL2008 / GTL2107) 12-Bit GTL to LVTTL Transistor
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 20 Seiten
GTL2008 Datasheet, Funktion
www.DataSheet4U.com
GTL2008; GTL2107
12-bit GTL to LVTTL translator with power good control and
high-impedance LVTTL and GTL outputs
Rev. 02 — 26 September 2006
Product data sheet
1. General description
The GTL2008/GTL2107 is a customized translator between dual Xeon processors,
Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals.
Functionally and footprint identical to the GTL2007, the GTL2008/GTL2107 LVTTL and
GTL outputs were changed to put them into a high-impedance state when EN1 and EN2
are LOW, with the exception of 11BO because its normal state is LOW, so it is forced
LOW. EN1 and EN2 will remain LOW until VCC is at normal voltage, the other inputs are in
valid states and VREF is at its proper voltage to assure that the outputs will remain
high-impedance through power-up.
Both the GTL2008/GTL2107 and the GTL2007 are derived from the GTL2006. They add
an enable function that disables the error output to the monitoring agent for platforms that
monitor the individual error conditions from each processor. This enable function can be
used so that false error conditions are not passed to the monitoring agent when the
system is unexpectedly powered down. This unexpected power-down could be from a
power supply overload, a CPU thermal trip, or some other event of which the monitoring
agent is unaware.
A typical implementation would be to connect each enable line to the system power good
signal or the individual enables to the VRD power good for each processor.
Typically Xeon processors specify a VTT of 1.1 V to 1.2 V, as well as a nominal Vref of
0.73 V to 0.76 V. To allow for future voltage level changes that may extend Vref to 0.63 of
VTT (minimum of 0.693 V with VTT of 1.1 V) the GTL2008/GTL2107 allows a minimum Vref
of 0.66 V. Characterization results show that there is little DC or AC performance variation
between these levels.
The GTL2008 is the companion chip to the GTL2009 3-bit GTL Front-Side Bus frequency
comparator that is used in dual-processor Xeon applications.
The GTL2107 is the Intel designation for the GTL2008.
2. Features
I Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver
I EN1 and EN2 disable error output
I All LVTTL and GTL outputs are put in a high-impedance state when EN1 and EN2 are
LOW
I 3.0 V to 3.6 V operation
I LVTTL I/O not 5 V tolerant
DataSheet4 U .com






GTL2008 Datasheet, Funktion
www.DataSheet4U.com
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
Table 7. SMI signals
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
Inputs
10AI1/10AI2
EN2
9BI
L HL
L HH
HHL
HHH
LLX
HL X
Output
10BO1/10BO2
L
L
L
H
L
H
Table 8. PROCHOT signals
H = HIGH voltage level; L = LOW voltage level.
Input
Input/output
5BI/6BI
5A/6A (open-drain)
LL
H L[2]
HH
Output
7BO1/7BO2
H[1]
L
H
[1] The enable on 7BO1/7BO2 includes a delay that prevents the transient condition where 5BI/6BI go from
LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a low glitch on the
7BO1/7BO2 outputs.
[2] Open-drain input/output terminal is driven to logic LOW state by other driver.
Table 9. NMI signals
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
Inputs
Input/output
11BI EN2 11A (open-drain)
L HH
L H L[1]
HHL
XL H
X L L[1]
Output
11BO
L
H
H
L
H
[1] Open-drain input/output terminal is driven to logic LOW state by other driver.
GTL2008_GTL2107_2
Product data sheet
DataSheet4 U .com
Rev. 02 — 26 September 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
6 of 20

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GTL2008 pdf, datenblatt
www.DataSheet4U.com
Philips Semiconductors
GTL2008; GTL2107
GTL translator with power good control and high-impedance outputs
12.1 Waveforms
VM = 1.5 V at VCC 3.0 V for A ports; VM = Vref for B ports.
tp
VM
VOH
VM
0V
002aaa999
VM = 1.5 V for A port and Vref for B port
a. Pulse duration
Fig 4. Voltage waveforms
input
output
1.5 V
tPLH
Vref
3.0 V
1.5 V
0V
tPHL
VTT
Vref
VOL
002aab000
A port to B port
b. Propagation delay times
input
output
Vref
tPLH
1.5 V
VTT
Vref
tPHL
1/3VTT
VOH
1.5 V
VOL
002aab001
PRR 10 MHz; Zo = 50 ; tr 2.5 ns; tf 2.5 ns
Fig 5. Propagation delay, 9BI to 9AO
input
output
Vref
tPLH
Vref
Vref
tPHL
VTT
1/3VTT
VTT
Vref
VOL
002aac195
Fig 7. 5BI to 7BO1 or 6BI to 7BO2
input
Vref
tPZL
output
1.5 V
Vref
tPLZ
VTT
1/3VTT
VCC
VOL + 0.3 V
002aab002
Fig 6. nBI to nA (I/O) or nBI to nAO open-drain outputs
input
output
1.5 V
tPLZ
1.5 V
tPZL
3.0 V
0V
VOL + 0.3 V
VOH
1.5 V
VOL
002aab005
Fig 8. EN1 to 5A (I/O) or EN2 to 6A (I/O) or EN1 to nAO
or EN2 to nAO
GTL2008_GTL2107_2
Product data sheet
DataSheet4 U .com
Rev. 02 — 26 September 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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