PDF DDC232 Data sheet ( Hoja de datos )

Número de pieza	DDC232
Descripción	Current-Input Analog-to-Digital Converter
Fabricantes	Burr-Brown
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No Preview Available ! www.DataSheet4U.com BurrĆBrown Products from Texas Instruments DDC232 SBAS331C – AUGUST 2004 – REVISED SEPTEMBER 2006 32-Channel, Current-Input Analog-to-Digital Converter FEATURES • SINGLE-CHIP SOLUTION TO DIRECTLY MEASURE 32 LOW-LEVEL CURRENTS • HIGH-PRECISION, TRUE INTEGRATING FUNCTION • INTEGRAL LINEARITY: ±0.025% of Reading ±1.0ppm of FSR • VERY LOW NOISE: 5.3ppm of FSR • LOW POWER: 7mW/channel • ADJUSTABLE FULL-SCALE RANGE • ADJUSTABLE DATA RATE: Up to 6kSPS – Integration Times Down to 166.5µs • DAISY-CHAINABLE SERIAL INTERFACE APPLICATIONS • CT SCANNER DAS • PHOTODIODE SENSORS • X-RAY DETECTION SYSTEMS Protected by US Patent #5841310 DESCRIPTION The DDC232 is a 20-bit, 32-channel, current-input analog-to-digital (A/D) converter. It combines both current-to-voltage and A/D conversion so that 32 separate low-level current output devices, such as photodiodes, can be directly connected to its inputs and digitized. For each of the 32 inputs, the DDC232 provides a dual-switched integrator front-end. This configuration allows for continuous current integration: while one integrator is being digitized by the onboard A/D converter, the other is integrating the input current. Adjustable integration times range from 166µs to 1s, allowing currents from fAs to µAs to be continuously measured with outstanding precision. The DDC232 has a serial interface designed for daisy-chaining in multi-device systems. Simply connect the output of one device to the input of the next to create the chain. Common clocking feeds all the devices in the chain so that the digital overhead in a multi-DDC232 system is minimal. The DDC232 uses a +5V analog supply and a +2.7V to +3.6V digital supply. Operating over the temperature range of 0°C to +70°C, the DDC232 is offered in a BGA-64 package. IN1 Dual Swit ched Integrator IN2 Dual Swit ched Integrator IN3 Dual Swit ched Integrator IN4 Dual Swit ched Integrator AVDD VREF DVDD ∆Σ Modulator Digital Filter Configuration and Control CLK CONV DIN_CFG CLK_CFG RESET ∆Σ Modulator Digital Filter DVALID IN29 Dual Swit ched Integrator IN30 Dual Swit ched Integrator IN31 Dual Swit ched Integrator IN32 Dual Swit ched Integrator ∆Σ Modulator Digital Filter Serial Interface DCLK DOUT ∆Σ Modulator Digital Filter DIN AGND DGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2006, Texas Instruments Incorporated 1 page www.ti.com Top View DDC232 SBAS331C – AUGUST 2004 – REVISED SEPTEMBER 2006 PIN CONFIGURATION Columns HGF EDCB A IN21 IN22 IN23 IN24 IN25 IN26 IN27 IN28 1 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 2 IN17 IN18 IN19 IN20 IN29 IN30 IN31 IN32 3 IN1 IN2 IN3 IN4 IN13 IN14 IN15 IN16 4 QGND AGND AGND AGND AGND AGND AGND AGND 5 AGND AVDD AVDD AVDD AGND DGND VREF VREF 6 DVALID DIN_CFG CLK_CFG DGND DGND RESET DVDD DGND 7 DCLK DGND CLK NC DOUT DGND DIN CONV 8 BGA PIN IN1–32 QGND AGND DGND AVDD VREF DVALID DIN_CFG CLK_CFG RESET DVDD CONV DIN DOUT NC CLK DCLK LOCATION Rows 1–4 H5 G5, F5, E5, D5, C5, B5, A5, D6, H6 A7, C6, D7, E7, C8, G8 E6, F6, G6 A6, B6 H7 G7 F7 C7 B7 A8 B8 D8 E8 F8 H8 PIN DESCRIPTIONS FUNCTION Analog Input Analog Analog Digital Analog Analog Input Digital Output Digital Input Digital Input Digital Input Digital Digital Input Digital Input Digital Output No Connect Digital Input Digital Input DESCRIPTION Analog Inputs for Channels 1 to 32 Quiet Analog Ground Analog Ground Digital Ground Analog Power Supply, +5V Nominal External Voltage Reference Input, +4.096V Nominal Data Valid Output, Active Low Configuration Register Data Input Configuration Register Clock Input Digital Reset, Active Low Digital Power Supply, 3.3V Nominal Conversion Control Input; 0 = Integrate on Side B, 1 = Integrate on Side A Serial Data Input Serial Data Output Do not connect; must be left floating. Master Clock Input Serial Data Clock Input Submit Documentation Feedback 5 5 Page www.ti.com Frequency Response The frequency response of the DDC232 is set by the front end integrators and is that of a traditional continuous time integrator, as shown in Figure 7. By adjusting tINT, the user can change the 3dB bandwidth and the location of the notches in the response. The frequency response of the ∆Σ converter that follows the front end integrator is of no consequence because the converter samples a held signal from the integrators. That is, the input to the ∆Σ converter is always a DC signal. Since the output of the front end integrators are sampled, aliasing can occur. Whenever the frequency of the input signal exceeds one-half of the sampling rate, the signal will fold back down to lower frequencies. 0 −10 −20 −30 −40 −50 0.1 t INT 1 10 t INT t INT Frequency 100 t INT DDC232 SBAS331C – AUGUST 2004 – REVISED SEPTEMBER 2006 CONFIGURATION REGISTER Some aspects of device operation are controlled by the onboard configuration register. The DIN_CFG, CLK_CFG, and RESET pins are used to write to this register. When beginning a write operation, hold CONV low and strobe RESET; see Figure 8. Then begin shifting in the configuration data on DIN_CFG. Data is written to the configuration register most significant bit first. The data is internally latched on the falling edge of CLK_CFG. Partial writes to the configuration register are not allowed—make sure to send all 12 bits when updating the register. Optional readback of the configuration register is available immediately after the write sequence. During readback, the 12-bit configuration data followed by a 4-bit revision id and the test pattern are shifted out on the DOUT pin on the rising edge of DCLK. NOTE: with Format = 1, the test pattern is 304 bits with only the last 72 bits non-zero. This sequence of outputs is repeated twice for each DDC232 and daisy-chaining is supported in configuration readback. Table 2 shows the test pattern configuration during readback. Table 3 shows the timing for the configuration register read and write operations. Strobe CONV to begin normal operation. Table 2. Test Pattern During Readback Format BIT 0 1 TEST PATTERN (Hex) 30F066012480F6h 30F066012480F69055h TOTAL READBACK BITS 512 640 Figure 7. TFrequency Response Submit Documentation Feedback 11 11 Page

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