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PDF ADL5310 Data sheet ( Hoja de datos )
| Número de pieza | ADL5310 | |
| Descripción | Dual Logarithmic Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
2 independent channels optimized for photodiode
interfacing
6-decade input dynamic range
Law conformance 0.3 dB from 3 nA to 3 mA
Temperature-stable logarithmic outputs
Nominal slope 10 mV/dB (200 mV/dec), externally scalable
Intercepts may be independently set by external resistors
User-configurable output buffer amplifiers
Single- or dual-supply operation
Space-efficient, 24-lead 4 mm × 4 mm LFCSP
Low power: < 10 mA quiescent current
APPLICATIONS
Gain and absorbance measurements
Multichannel power monitoring
General-purpose baseband log compression
PRODUCT DESCRIPTION
The ADL53101 low cost, dual logarithmic amplifier converts
input current over a wide dynamic range to a linear-in-dB
output voltage. It is optimized to determine the optical power
in wide-ranging optical communication system applications,
including control circuitry for lasers, optical switches, atten-
uators, and amplifiers, as well as system monitoring. The device
is equivalent to a dual AD8305 with enhanced dynamic range
(120 dB). While the ADL5310 contains two independent signal
channels with individually configurable transfer function
constants (slope and intercept), internal bias circuitry is shared
between channels for improved power consumption and
channel matching. Dual converters in a single, compact LFCSP
package yield space-efficient solutions for measuring gain or
attenuation across optical elements. Only a single supply is
required; optional dual-supply operation offers added flexibility.
The ADL5310 employs an optimized translinear structure that
use the accurate logarithmic relationship between a bipolar
transistor’s base emitter voltage and collector current, with
appropriate scaling by precision currents to compensate for the
inherent temperature dependence. Input and reference current
pins sink current ranging from 3 nA to 3 mA (limited to ±60 dB
between input and reference) into a fixed voltage defined by the
VSUM potential. The VSUM potential is internally set to
500 mV but may be externally grounded for dual-supply opera-
tion, and for additional applications requiring voltage inputs.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
120 dB Range (3 nA to 3 mA)
Dual Logarithmic Converter
ADL5310
FUNCTIONAL BLOCK DIAGRAM
VSUM
665kΩ
VREF VRDZ
COMM
OUT1
VOUT1
IRF1
VBIAS
VNEG
6.69kΩ
TEMPERATURE ILOG
COMPENSATION
IPD1 INP1
14.2kΩ
0.5V
2.5V REFERENCE
20kΩ
80kΩ
GENERATOR
COMM
IRF2
VBIAS
VNEG
14.2kΩ
TEMPERATURE ILOG
COMPENSATION
IPD2 INP2
VSUM
665kΩ
VREF
6.69kΩ
COMM
Figure 1.
SCL1
BIN1
451Ω LOG1
OUT2
VOUT2
SCL2
BIN2
451Ω LOG2
The logarithmic slope is set to 10 mV/dB (200 mV/decade)
nominal and can be modified using external resistors and the
independent buffer amplifiers. The logarithmic intercepts for
each channel are defined by the individual reference currents,
which are set to 3 μA nominal for maximum input range by
connecting 665 kΩ resistors between the 2.5 V VREF pins and
the IRF1 and IRF2 inputs. Tying VRDZ to VREF effectively sets
the x-intercept four decades below the reference current—
typically 300 pA for a 3 µA reference.
The use of individually optimized reference currents may
be valuable when using the ADL5310 for gain or absorbance
measurements where each channel input has a different current-
range requirement. The reference current inputs
are also fully functional dynamic inputs, allowing log ratio
operation with the reference input current as the denominator.
The ADL5310 is specified for operation from –40°C to +85°C.
1 US Patents: 4,604,532, 5,519,308. Other patents pending.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADL5310
24 23 22 21 20 19
VSUM 1
INP1 2
IRF1 3
IRF2 4
INP2 5
VSUM 6
PIN 1
INDICATOR
ADL5310
DUAL LOG AMP
TOP VIEW
(Not to Scale)
18 SCL1
17 BIN1
16 LOG1
15 LOG2
14 BIN2
13 SCL2
7 8 9 10 11 12
Figure 2. 24-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Function
1, 6
VSUM
Guard Pin. Used to shield the INP1 and INP2 input current lines, and for optional adjustment of the input
summing node potentials. Pin 1 and Pin 6 are internally shorted.
2 INP1 Channel 1 Numerator Input. Accepts (sinks) photodiode current IPD1. Usually connected to photodiode anode
such that photocurrent flows into INP1.
3 IRF1 Channel 1 Denominator Input. Accepts (sinks) reference current, IRF1.
4 IRF2 Channel 2 Denominator Input. Accepts (sinks) reference current, IRF2.
5 INP2 Channel 2 Numerator Input. Accepts (sinks) photodiode current IPD2. Usually connected to photodiode anode
such that photocurrent flows into INP2.
7, 24 VREF
Reference Output Voltage of 2.5 V. Pin 7 and Pin 24 are internally shorted.
8, 9
VPOS
Positive Supply, (VP – VN) ≤ 12 V. Both pins must be connected externally.
10, 11, 20 VNEG
Optional Negative Supply, VN. These pins are usually grounded. For more details, see the General Structure and
Applications sections. All VNEG pins must be connected externally.
12
OUT2
Buffer Output for Channel 2.
13
SCL2
Buffer Amplifier Inverting Input for Channel 2.
14 BIN2 Buffer Amplifier Noninverting Input for Channel 2.
15
LOG2
Output of the Logarithmic Front End for Channel 2.
16
LOG1
Output of the Logarithmic Front End for Channel 1.
17 BIN1 Buffer Amplifier Noninverting Input for Channel 1.
18
SCL1
Buffer Amplifier Inverting Input for Channel 1.
19
OUT1
Buffer Output for Channel 1.
21, 22
COMM
Analog Ground. Pin 21 and Pin 22 are internally shorted.
23
VRDZ
Intercept Shift Reference Input. The top of a resistive divider network that offsets VLOG to position the
intercept. Normally connected to VREF; may also be connected to ground when bipolar outputs are to be
provided.
Rev. A | Page 5 of 20
5 Page 
ADL5310
GENERAL STRUCTURE
The ADL5310 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems and is
useful in many nonoptical applications. These notes explain the
structure of this unique style of translinear log amp. Figure 33
shows the key elements of one of the two identical on-board
log amps.
BIAS
GENERATOR
PHOTODIODE
INPUT 2.5V
CURRENT
80kΩ
IPD 0.5V
IREF
VREF
IREF
20kΩ
COMM
INP1
(INP2)
VSUM
0.5V
0.5V
Q1
VBE1 Q2
VBE1
VBE2
TEMPERATURE
COMPENSATION
(SUBTRACT AND
DIVIDE BY T°K)
44µA/dec
14.2kΩ 451Ω
VRDZ
VLOG
VBE2 6.69kΩ
VNEG (NORMALLY GROUNDED)
COMM
Figure 33. Simplified Schematic of Single Log Amp
The photodiode current IPD is received at either Pin INP1 or
Pin INP2. The voltages at these nodes are approximately equal
to the voltage on the adjacent guard pins, VSUM, as well as
reference inputs IRF1 and IRF2, due to the low offset voltage
of the JFET operational amplifiers. Transistor Q1 converts IPD
to a corresponding logarithmic voltage, as shown in Equation 1.
A finite positive value of VSUM is needed to bias the collector of
Q1 for the usual case of a single-supply voltage. This is inter-
nally set to 0.5 V, one-fifth of the 2.5 V reference voltage that
appears on Pin VREF. Both VREF pins are internally shorted,
as are both VSUM pins. The resistance at the VSUM pin is
nominally 16 kΩ; this voltage is not intended as a general bias
source.
The ADL5310 also supports the use of an optional negative
supply voltage, VN, at Pin VNEG. When VN is 0.5 V or more
negative, VSUM may be connected to ground; thus, INP1, INP2,
IRF1, and IRF2 assume this potential. This allows operation as a
voltage-input logarithmic converter by the inclusion of a series
resistor at either or both inputs. Note that the resistor setting IREF
for each channel needs to be adjusted to maintain the intercept
value. Also note that the collector-emitter voltages of Q1 and Q2
are the full VN and effects due to self-heating cause errors at
large input currents.
The input-dependent VBE1 of Q1 is compared with the reference
VBE2 of a second transistor, Q2, operating at IREF. IREF is gener-
ated externally to a recommended value of 3 µA. However, other
values over a several-decade range can be used with a slight
degradation in law conformance.
THEORY
The base-emitter voltage of a bipolar junction transistor (BJT)
can be expressed by Equation 1, which immediately shows its
basic logarithmic nature:
VBE = kT/q ln(IC/IS)
(1)
where:
IC is the collector current.
IS is a scaling current, typically only 10–17 A.
kT/q is the thermal voltage, proportional to absolute
temperature (PTAT), and is 25.85 mV at 300 K.
IS is never precisely defined and exhibits an even stronger tem-
perature dependence, varying by a factor of roughly a billion
between −35°C and +85°C. Thus, to make use of the BJT as an
accurate logarithmic element, both of these temperature
dependencies must be eliminated.
The difference between the base-emitter voltages of a matched
pair of BJTs, one operating at the photodiode current IPD and the
other operating at a reference current IREF, can be written as
VBE1 – VBE2 = kT/q ln(IPD/IS) – kT/q ln(IREF/IS)
= ln(10) kT/q log10(IPD/IREF)
= 59.5 mV log10(IPD/IREF) (T = 300 K)
(2)
The uncertain, temperature-dependent saturation current, IS,
that appears in Equation 1 has therefore been eliminated. To
eliminate the temperature variation of kT/q, this difference
voltage is processed by what is essentially an analog divider.
Effectively, it puts a variable under Equation 2. The output of
this process, which also involves a conversion from voltage
mode to current mode, is an intermediate, temperature-
corrected current:
ILOG = IY log10(IPD/IREF)
(3)
where IY is an accurate, temperature-stable scaling current that
determines the slope of the function (change in current per
decade). For the ADL5310, IY is 44 µA, resulting in a
temperature-independent slope of 44 µA/decade for all values
of IPD and IREF. This current is subsequently converted back to a
voltage-mode output, VLOG, scaled 200 mV/decade.
It is apparent that this output should be 0 for IPD = IREF and
would need to swing negative for smaller values of input
current. To avoid this, IREF would need to be as small as the
smallest value of IPD. Accordingly, an offset voltage is added to
VLOG to shift it upward by 0.8 V when VRDZ is directly
connected to VREF. This moves the intercept to the left by four
decades (at 200 mV/decade), from 3 μA to 300 pA:
ILOG = IY log10(IPD/IINTC)
(4)
where IINTC is the operational value of the intercept current.
Because values of IPD < IINTC result in a negative VLOG, a negative
supply of sufficient value is required to accommodate this
situation.
Rev. A | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADL5310.PDF ] | |
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