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PDF ADIS16201 Data sheet ( Hoja de datos )
| Número de pieza | ADIS16201 | |
| Descripción | Programmable Dual-Axis | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Dual-axis inclinometer/accelerometer measurements
12-, 14-bit digital inclination/acceleration sensor outputs
+1.7 g accelerometer measurement range
+90o inclinometer measurement range, linear output
12-bit digital temperature sensor output
Digitally controlled sensitivity and bias calibration
Digitally controlled sample rate
Digitally controlled frequency response
Dual alarm settings with rate/threshold limits
Auxiliary digital I/O
Digitally activated self test
Digitally activated low power mode
SPI®-compatible serial interface
Auxiliary 12-bit ADC input and DAC output
Single-supply operation: 3.0 V to +3.6 V
3500 g powered shock survivability
APPLICATIONS
Platform control, stabilization, and leveling
Tilt sensing, inclinometers
Motion/position measurement
Monitor/alarm devices (security, medical, safety)
GENERAL DESCRIPTION
The ADIS16201 is a complete, dual-axis acceleration and
inclination angle measurement system available in a single
compact package enabled by the Analog Devices iSensor™
integration. By enhancing the Analog Devices iMEMS® sensor
technology with an embedded signal processing solution, the
ADIS16201 provides factory calibrated and tunable digital
sensor data in a convenient format that can be accessed using a
serial peripheral interface (SPI). The SPI interface provides
access to measurements for dual-axis linear acceleration, dual-
axis linear inclination angle, temperature, power supply, and
one auxiliary analog input. Easy access to calibrated digital
sensor data provides developers with a system-ready device,
reducing development time, cost, and program risk.
Unique characteristics of the end system are accommodated
easily through several built-in features, such as a single
command in-system offset calibration, along with convenient
sample rate and bandwidth control.
Programmable Dual-Axis
Inclinometer/Accelerometer
ADIS16201
FUNCTIONAL BLOCK DIAGRAM
AUX AUX
ADC DAC VREF
ADIS16201
TEMPERATURE
SENSOR
DUAL-AXIS
ACCELEROMETER
SELF-TEST
SIGNAL
CONDITIONING
AND
CONVERSION
CALIBRATION
AND
DIGITAL
PROCESSING
DIGITAL
CONTROL
SPI
PORT
CS
SCLK
DIN
DOUT
VDD
COM
POWER
MANAGEMENT
ALARMS
AUXILIARY
I/O
RST
Figure 1.
DIO0 DIO1
The ADIS16201 offers the following embedded features, which
eliminate the need for external circuitry and provide a simplified
system interface:
• Configurable alarm function
• Auxiliary 12-bit ADC
• Auxiliary 12-bit DAC
• Configurable digital I/O port
• Digital self-test function
The ADIS16201 offers two power management features for
managing system-level power dissipation: low power mode and
a configurable shutdown feature.
The ADIS16201 is available in a 9.2 mm × 9.2 mm × 3.9 mm
laminate-based land grid array (LGA) package with a
temperature range of −40°C to +125°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.
Table 2.
Parameter
Description
fSCLK
tDATARATE
tDATARATE
tcs
tDAV
tDSU
tDHD
tDF
tDR
tSFS
Fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz)
Normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz)
Chip select period, fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz)
Chip select period, normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz)
Chip select to clock edge
Data output valid after SCLK edge
Data input setup time before SCLK rising edge
Data input hold time after SCLK rising edge
Data output fall time
Data output rise time
CS high after SCLK edge
1 Guaranteed by design, not tested.
Min1
0.01
0.01
40
100
48.8
24.4
48.8
5
TIMING DIAGRAMS
CS
SCLK
tDATA RATE
tSTALL
tSTALL = tDATA RATE – 16/fSCLK
Figure 2. SPI Chip Select Timing
ADIS16201
Typ Max Unit
2.5 MHz
1.0 MHz
μs
μs
ns
100 ns
ns
ns
5 12.5 ns min
5 12.5 ns min
ns typ
CS
SCLK
DOUT
DIN
tCS
1
MSB
W/R
23 4 56
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A5 A4 A3 A2
15 16
tSFS
DB2
DB1
LSB
D2 D1 LSB
Figure 3. SPI Timing
(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
Rev. A | Page 5 of 32
5 Page 
5
4
3
2
1
0
–1
–2
–3
–4
–5
0
250
3.0V/–40°C
3.0V/+25°C
3.0V/+125°C
3.3V /–40°C
3.3V/+25°C
3.3V/+125°C
3.6V/–40°C
3.6V/+25°C
3.6V/+125°C
512 1024 1536 2048 2560 3072 3584 4096
DAC STATE
Figure 23. Typical DAC Integral Nonlinearity
200
150
100
50
0
(V)
Figure 24. VREF Distribution at 25°C/3.3 V
60
50
40
30
20
10
0
(°C)
Figure 25. Temperature Distribution at 25°C/3.3 V
ADIS16201
140
120
100
80
60
40
20
0
(mA)
Figure 26. Normal Mode Power Supply Current Distribution at 25°C/3.3 V
140
120
100
80
60
40
20
0
(mA)
Figure 27. Fast Mode Power Supply Current Distribution at 25°C/3.3 V
180
160
140
120
100
80
60
40
20
0
(µA)
Figure 28. Sleep Mode Power Supply Current Distribution at 25°C/3.3 V
Rev. A | Page 11 of 32
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet ADIS16201.PDF ] | |
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