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ADE7760 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADE7760
Beschreibung Energy Metering IC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
ADE7760 Datasheet, Funktion
www.DataSheet4U.com
FEATURES
High accuracy active energy measurement IC, supports
IEC 687/61036
Less than 0.1% error over a dynamic range of 500 to 1
Supplies active power on the frequency outputs F1 and F2
High frequency output CF is intended for calibration and
supplies instantaneous active power
Continuous monitoring of the phase and neutral current
allows fault detection in 2-wire distribution systems
Current channels input level best suited for current
transformer sensors
Uses the larger of the two currents (phase or neutral) to
bill—even during a fault condition
Two logic outputs (FAULT and REVP) can be used to indicate
a potential miswiring or fault condition
Direct drive for electromechanical counters and 2-phase
stepper motors (F1 and F2)
Proprietary ADCs and DSP provide high accuracy over large
variations in environmental conditions and time
Reference 2.5 V ± 8% (drift 30 ppm/°C typical) with external
overdrive capability
Single 5 V supply, low power
Energy Metering IC with
On-Chip Fault Detection
ADE7760
GENERAL DESCRIPTION
The ADE7760 is a high accuracy, fault tolerant, electrical energy
measurement IC intended for use with 2-wire distribution
systems. The part specifications surpass the accuracy require-
ments as quoted in the IEC61036 standard.
The only analog circuitry used on the ADE7760 is in the ADCs
and reference circuit. All other signal processing (such as multi-
plication and filtering) is carried out in the digital domain. This
approach provides superior stability and accuracy over extremes
in environmental conditions and over time.
The ADE7760 incorporates a fault detection scheme similar to
the ADE7751 by continuously monitoring both the phase and
neutral currents. A fault is indicated when these currents differ
by more than 6.25%.
The ADE7760 supplies average active power information on the
low frequency outputs F1 and F2. The CF logic output gives
instantaneous active power information.
The ADE7760 includes a power supply monitoring circuit on
the VDD supply pin. Internal phase-matching circuitry ensures
that the voltage and current channels are matched. An internal
no-load threshold ensures that the ADE7760 does not exhibit
any creep when there is no load.
V1A 2
V1N 4
V1B 3
V2P 6
V2N 5
AGND
8
FUNCTIONAL BLOCK DIAGRAM
FAULT
15
VDD
1
POWER
SUPPLY MONITOR
ADE7760
SIGNAL PROCESSING BLOCK
ADC
A>B
HPF
ADC
B>A
A<>B
ADC
LPF
2.5V
4k
REFERENCE
INTERNAL
OSCILLATOR
DIGITAL-TO-FREQUENCY CONVERTER
9
REFIN/OUT
14
RCLKIN
17
DGND
10 11 12 16 18 19 20
SCF S1 S0 REVP CF F2 F1
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






ADE7760 Datasheet, Funktion
ADE7760
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to AGND
Analog Input Voltage to AGND
V1AP, V1BP, V1N, V2N, V2P
Reference Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature
20-Lead SSOP, Power Dissipation
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 s)
Infrared (15 s)
Rating
–0.3 V to +7 V
–6 V to +6 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–40°C to +85°C
–65°C to +150°C
150°C
450 mW
112°C/W
215°C
220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 24

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ADE7760 pdf, datenblatt
ADE7760
RF
±660mV CF
RF
AGND
CF
V2P
V2N
RA*
RB*
VR*
*RB + VR = RF
CF
V2P
RF
CT
V2N
Figure 12. Typical Connection for Channel 2
INTERNAL OSCILLATOR
The nominal internal oscillator frequency is 450 kHz when
used with the recommended ROSC resistor value of 6.2 kΩ
between RCLKIN and DGND (see Figure 13).
The internal oscillator frequency is inversely proportional to the
value of this resistor. Although the internal oscillator operates
when used with a ROSC resistor value between 5 kΩ and 12 kΩ, it
is recommended to choose a value within the range of the
nominal value.
The output frequencies on CF, F1, and F2 are directly
proportional to the internal oscillator frequency; thus, the
resistor ROSC must have a low tolerance and low temperature
drift. A low tolerance resistor limits the variation of the internal
oscillator frequency. Small variation of the clock frequency and
consequently of the output frequencies from meter to meter
contributes to a smaller calibration range of the meter. A low
temperature drift resistor directly limits the variation of the
internal clock frequency over temperature. The stability of the
meter to external variation is then better ensured by design.
ADE7760
2.5V
4k
REFERENCE
INTERNAL
OSCILLATOR
9
REFIN/OUT
14
RCLKIN
ROSC
17
DGND
Figure 13. ADE7760 Internal Oscillator Connection
ANALOG-TO-DIGITAL CONVERSION
The analog-to-digital conversion in the ADE7760 is carried out
using second-order Σ-Δ ADCs. Figure 14 shows a first-order
(for simplicity) Σ-Δ ADC. The converter is made up of two
parts, the Σ-Δ modulator and the digital low-pass filter.
ANALOG
LOW-PASS FILTER
R
C
MCLK
INTEGRATOR
VREF
LATCHED
DIGITAL
COMPAR- LOW-PASS FILTER
ATOR
1 24
....10100101....
1-BIT DAC
Figure 14. First-Order Σ-∆ ADC
A Σ-Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7760, the sampling clock is equal to CLKIN.
The 1-bit DAC in the feedback loop is driven by the serial data
stream. The DAC output is subtracted from the input signal. If
the loop gain is high enough, the average value of the DAC
output (and, therefore, the bit stream) approaches that of the
input signal level. For any given input value in a single sampling
interval, the data from the 1-bit ADC is virtually meaningless.
Only when a large number of samples are averaged is a
meaningful result obtained. This averaging is carried out in the
second part of the ADC, the digital low-pass filter. By averaging
a large number of bits from the modulator, the low-pass filter
can produce 24-bit data words that are proportional to the input
signal level.
The Σ-Δ converter uses two techniques to achieve high resolu-
tion from what is essentially a 1-bit conversion technique. The
first is oversampling, which means that the signal is sampled at
a rate (frequency) that is many times higher than the bandwidth
of interest. For example, the sampling rate in the ADE7760 is
CLKIN (450 kHz) and the band of interest is 40 Hz to 1 kHz.
Oversampling has the effect of spreading the quantization noise
(noise due to sampling) over a wider bandwidth. With the noise
spread more thinly over a wider bandwidth, the quantization
noise in the band of interest is lowered (see Figure 15).
However, oversampling alone is not an efficient enough method
to improve the signal-to-noise ratio (SNR) in the band of inter-
est. For example, an oversampling ratio of 4 is required just to
increase the SNR by only 6 dB (1 bit). To keep the oversampling
ratio at a reasonable level, it is possible to shape the quantization
noise so that the majority of the noise lies at the higher frequen-
cies. This is what happens in the Σ-Δ modulator; the noise is
shaped by the integrator, which has a high-pass type response
for the quantization noise. The result is that most of the noise is
at the higher frequencies where it can be removed by the digital
low-pass filter. This noise shaping is also shown in Figure 15.
Rev. 0 | Page 12 of 24

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