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AD9230 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9230
Beschreibung 1.8 V Analog-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9230 Datasheet, Funktion
12-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Analog-to-Digital Converter
AD9230
FEATURES
SNR = 64.9 dBFS @ fIN up to 70 MHz @ 250 MSPS
ENOB of 10.4 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
SFDR = −79 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
Excellent linearity
DNL = ±0.3 LSB typical
INL = ±0.5 LSB typical
LVDS at 250 MSPS (ANSI-644 levels)
700 MHz full power analog bandwidth
On-chip reference, no external decoupling required
Integrated input buffer and track-and-hold
Low power dissipation
434 mW @ 250 MSPS—LVDS SDR mode
400 mW @ 250 MSPS—LVDS DDR mode
Programmable input voltage range
1.0 V to 1.5 V, 1.25 V nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
GENERAL DESCRIPTION
The AD9230 is a 12-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates at up to a 250 MSPS conversion
rate and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary
functions, including a track-and-hold (T/H) and voltage
reference, are included on the chip to provide a complete signal
conversion solution.
The ADC requires a 1.8 V analog voltage supply and a
differential clock for full performance operation. The digital
outputs are LVDS (ANSI-644) compatible and support either
twos complement, offset binary format, or Gray code. A data
clock output is available for proper output data timing.
Fabricated on an advanced CMOS process, the AD9230 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C).
CML
VIN+
VIN–
CLK+
CLK–
FUNCTIONAL BLOCK DIAGRAM
RBIAS PWDN
AGND
AVDD (1.8V)
REFERENCE
AD9230
TRACK-AND-HOLD
CLOCK
MANAGEMENT
ADC 12
12-BIT
CORE
SERIAL PORT
OUTPUT 12
STAGING
LVDS
RESET SCLK SDIO CSB
Figure 1. Functional Block Diagram
DRVDD
DRGND
D11 TO D0
OR+
OR–
DCO+
DCO–
PRODUCT HIGHLIGHTS
1. High Performance—Maintains 64.9 dBFS SNR @ 250 MSPS
with a 70 MHz input.
2. Low Power—Consumes only 434 mW @ 250 MSPS.
3. Ease of Use—LVDS output data and output clock signal
allow interface to current FPGA technology. The on-chip
reference and sample and hold provide flexibility in system
design. Use of a single 1.8 V supply simplifies system
power supply design.
4. Serial Port Control—Standard serial port interface supports
various product functions, such as data formatting, disabling
the clock duty cycle stabilizer, power-down, gain adjust,
and output test pattern generation.
5. Pin-Compatible Family—10-bit pin-compatible family
offered as AD9211.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.






AD9230 Datasheet, Funktion
AD9230
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
(Differential)
Input Capacitance
LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current (SDIO)
Logic 0 Input Current (SDIO)
Logic 1 Input Current
(SCLK, PDWN, CSB, RESET)
Logic 0 Input Current
(SCLK, PDWN, CSB, RESET)
Input Capacitance
LOGIC OUTPUTS2
VOD Differential Output Voltage
VOS Output Offset Voltage
Output Coding
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
AD9230-170
Min Typ Max
AD9230-210
Min Typ Max
AD9230-250
Min Typ Max
CMOS/LVDS/LVPECL
1.2
0.2 6
AVDD −
0.3
AVDD +
1.6
1.1 AVDD
1.2 3.6
0 0.8
−10 +10
−10 +10
16 20 24
CMOS/LVDS/LVPECL
1.2
0.2 6
AVDD −
0.3
AVDD +
1.6
1.1 AVDD
1.2 3.6
0 0.8
−10 +10
−10 +10
16 20 24
CMOS/LVDS/LVPECL
1.2
0.2 6
AVDD −
0.3
AVDD +
1.6
1.1 AVDD
1.2 3.6
0 0.8
−10 +10
−10 +10
16 20 24
4 44
0.8 ×
VDD
0.2 ×
AVDD
0
−60
55
0
4
0.8 ×
VDD
0.8 ×
VDD
0.2 ×
AVDD
0
−60
55
0
4
0.2 ×
AVDD
0
−60
50
0
4
247
1.125
454 247
454 247
1.375 1.125
1.375 1.125
Twos complement, Gray code, or offset binary (default)
454
1.375
Unit
V
V p-p
V
V
V
V
μA
μA
pF
V
V
μA
μA
μA
μA
pF
mV
V
1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
2 LVDS RTERMINATION = 100 Ω.
Rev. 0 | Page 5 of 32

6 Page









AD9230 pdf, datenblatt
AD9230
D3/D9– 1
D3/D9+ 2
D4/D10– 3
D4/D10+ 4
(MSB) D5/D11– 5
(MSB) D5/D11+ 6
DRVDD 7
DRGND 8
OR– 9
OR+ 10
DNC 11
DNC 12
DNC 13
DNC 14
PIN 1
INDICATOR
AD9230
TOP VIEW
(Not to Scale)
PIN 0 (EXPOSED PADDLE) = AGND
42 AVDD
41 AVDD
40 CML
39 AVDD
38 AVDD
37 AVDD
36 VIN–
35 VIN+
34 AVDD
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
DNC = DO NOT CONNECT
Figure 5. Double Data Rate
Table 8. Double Data Rate Mode Pin Function Descriptions
Pin No.
Mnemonic Description
30, 32 to 34, 37 to 39, AVDD
41 to 43, 46
1.8 V Analog Supply.
7, 24, 47
DRVDD
1.8 V Digital Output Supply.
0
AGND1
Analog Ground.
8, 23, 48
DRGND1
Digital Output Ground.
35
VIN+
Analog Input—True.
36
VIN−
Analog Input—Complement.
40 CML Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
44
CLK+
Clock Input—True.
45
CLK−
Clock Input—Complement.
31
RBIAS
Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V.
28
RESET
CMOS-Compatible Chip Reset (Active Low).
25 SDIO/DCS Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode).
26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
27 CSB Serial Port Chip Select (Active Low).
29
PWDN
Chip Power-Down.
49
DCO−
Data Clock Output—Complement.
50
DCO+
Data Clock Output—True.
51
D0/D6−
D0/D6 Complement Output Bit (LSB).
52
D0/D6+
D0/D6 True Output Bit (LSB).
53
D1/D7−
D1/D7 Complement Output Bit.
54
D1/D7+
D1/D7 True Output Bit.
55
D2/D8−
D2/D8 Complement Output Bit.
56
D2/D8+
D2/D8 True Output Bit.
1
D3/D9−
D3/D9 Complement Output Bit.
2
D3/D9+
D3/D9 True Output Bit.
3
D4/D10−
D4/D10 Complement Output Bit.
4
D4/D10+
D4/D10 True Output Bit.
5
D5/D11−
D5/D11 Complement Output Bit (MSB).
6
D5/D11+
D5/D11 True Output Bit (MSB).
Rev. 0 | Page 11 of 32

12 Page





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