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ADAV400 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADAV400
Beschreibung Audio Codec
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 36 Seiten
ADAV400 Datasheet, Funktion
www.DataSheet4U.com
Audio Codec with
Embedded SigmaDSP® Processor
ADAV400
FEATURES
Fully programmable audio digital signal processing (DSP) for
enhanced sound processing
Scalable digital audio delay line
Pool of 400 ms @ 48 kHz (200 ms for stereo channel)
High performance, integrated analog-to-digital converters
(ADCs) and digital-to-analog converters (DACs)
1 stereo analog input (ADC)
4 stereo analog inputs with mux-to-stereo ADC
4 stereo (8-channel) analog outputs (DACs)
Dedicated headphone output with integrated amplifier
Multichannel digital I/O
8-channel I2S input and output modes
8- and 16-channel TDM input and output modes
2-channel (1 stereo) asynchronous I2S input with
integrated sample rate converter (SRC), supporting
sample rates from 5 kHz to 50 kHz
Features SigmaStudio™, a proprietary graphical
programming tool for fast development of custom
signal flows
Includes various third-party audio algorithms
I2C® control interface
Operates from 3.3 V (analog), 1.8 V (digital core),
3.3 V (digital interface)
Features on-chip regulator for single 3.3 V operation
80-lead LQFP package (14 mm × 14 mm)
Temperature range: 0°C to 70°C
APPLICATIONS
ATV and AV audio applications
TV audio processing
Set top box (STB)
HTiB
General audio enhancement
FUNCTIONAL BLOCK DIAGRAM
ADAV400
MCLKI
MCLKO
SCL
SDA
AD0
BCLK0
LRCLK0
SDIN0
SDIN1
SDIN2
SDIN3
AINL1
AINR1
AINL4
AINR4
PLL
SYSTEM
CLOCKS
I2C INTERFACE
SRC
ASYNCHRONIZE
DIGITAL INPUT
SYNCHRONIZE
MULTICHANNEL
DIGITAL INPUT
ADC
PROGRAMMABLE
AUDIO
PROCESSOR
CORE
A–V
SYNC DELAY
MEMORY
Figure 1.
MULTICHANNEL
DIGITAL OUTPUTS
DAC
DAC
DAC
DAC
SDO0
SDO1
SDO2
SDO3
LRCLK1
BCLK1
VOUT1
VOUT2
VOUT3
VOUT4
HPOUTL
HPOUTR
AUXL1
AUXR1
AUXL2
AUXR2
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






ADAV400 Datasheet, Funktion
ADAV400
DIGITAL TIMING
Table 2.
Parameter
MASTER CLOCK AND RESET
fMCLKI (MCLKI Frequency)
tMCH (MCLKI High)
tMCL (MCLKI Low)
tRLPW (RESET Low Pulse Width)
I2C PORT
fSCL (SCL Clock Frequency)
tSCLH (SCL High)
tSCLL (SCL Low)
Start Condition
tSCS (Setup Time)
tSCH (Hold Time)
tDS (Data Setup Time)
tSCR (SCL Rise Time)
tSCF (SCL Fall Time)
tSDR (SDA Rise Time)
tSDF (SDA Fall Time)
Stop Condition
tSCSH (Setup Time)
SERIAL PORTS
Slave Mode
tSBH (BCLKx High)
tSBL (BCLKx Low)
fSBF (BCLKx Frequency)
tSLS (LRCLKx Setup)
tSLH (LRCLKx Hold)
tSDS (SDINx Setup)
tSDH (SDINx Hold)
tSDD (SDOx Delay)
Master Mode
tMLD (LRCLKx Delay)
tMDD (SDOx Delay)
tMDS (SDINx Setup)
tMDH (SDINx Hold)
Min
3.024
10
10
20
0.6
1.3
0.6
0.6
100
0.6
Max
24.576
400
300
300
300
300
Unit Comments
MHz
ns
ns
ns
kHz
μs
μs
μs Relevant for repeated start condition
μs The first clock is generated after this period
ns
ns
ns
ns
ns
μs
40
40
64 × fS
10
10
10
10
10
10
40
5
40
ns
ns
ns To BCLK rising edge
ns From BCLK rising edge
ns To BCLK rising edge
ns From BCLK rising edge
ns From BCLK falling edge
ns From BCLK falling edge
ns From BCLK falling edge
ns From BCLK rising edge
ns From BCLK rising edge
Rev. 0 | Page 6 of 36

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ADAV400 pdf, datenblatt
ADAV400
0
–20
–40
–60
–80
–100
–120
–140
–160
0
DNR = 95dB
(A-WEIGHTED)
4000
8000
12000
FREQUENCY (Hz)
16000
Figure 12. DAC Dynamic Range
20000
0
THD + N = –94dB
–20 VIN = –3dBFS
–40
–60
–80
–100
–120
–140
–160
0
4000
8000
12000
FREQUENCY (Hz)
16000
Figure 13. DAC Total Harmonic Distortion + Noise
20000
0
–20
–40
–60
–80
–100
–120
–140
–160
0
DNR = 95dB
(A-WEIGHTED)
4000
8000
12000
FREQUENCY (Hz)
16000
Figure 14. ADC Dynamic Range
20000
0
THD + N = –93dB
–20 VIN = –3dBFS
–40
–60
–80
–100
–120
–140
–160
0
4000
8000
12000
FREQUENCY (Hz)
16000
Figure 15. ADC Total Harmonic Distortion + Noise
20000
0
–5
–10
–15
–20
0
0.1 0.2 0.3 0.4
FS (Normalized)
Figure 16. Sample Rate Converter Transfer Function
0.5
Rev. 0 | Page 12 of 36

12 Page





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