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DS3994 Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer DS3994
Beschreibung 4-Channel Cold Cathode Fluorescent Lamp Controller
Hersteller Maxim Integrated Products
Logo Maxim Integrated Products Logo 




Gesamt 28 Seiten
DS3994 Datasheet, Funktion
www.DataSheet4U.com
Rev 0; 10/06
4-Channel Cold-Cathode
Fluorescent Lamp Controller
General Description
The DS3994 is a 4-channel controller for cold-cathode
fluorescent lamps (CCFLs) that backlight liquid crystal
displays (LCDs) in TV and PC monitor applications. The
DS3994’s features make it suitable for use in even the
largest LCDs, while its low BOM cost makes it ideal for
the entire range of LCD TVs and monitors.
The DS3994 can stagger the lamp bursts from each of
the four channels. This feature allows scanning back-
light schemes for video quality improvement to be
implemented using a single CCFL controller IC, making
it very simple and inexpensive to provide this enhance-
ment. In addition, staggering the bursts from each
channel can be used to minimize current ripple on the
display power supply, which is especially important for
larger LCDs. The relative stagger between each of the
channels is programmable, so this feature can be tai-
lored to the specific application.
The DS3994 uses a push-pull drive architecture but it
can also support full and half bridge drive schemes.
Contact the factory for more details.
LCD Televisions
LCD PC Monitors
Applications
Pin Configurations
TOP VIEW
LOSC 1
A0 2
PSYNC 3
POSC 4
BRIGHT 5
SVM 6
GA1 7
GB1 8
LCM1 9
OVD1 10
GA2 11
GB2 12
LCM2 13
OVD2 14
DS3994
SO-300
28 LSYNC
27 FAULT
26 SCL
25 SDA
24 OVD4
23 LCM4
22 GB4
21 GA4
20 OVD3
19 LCM3
18 GB3
17 GA3
16 VCC
15 GND
Features
o High-Density CCFL Controller for LCD TV and
PC Monitor Backlights
o Programmable Staggered Start for Burst Dimming
on Each Channel
o Strike Frequency Boost Option
o Programmable Strike Time
o Can Be Easily Cascaded
o Minimal External Components
o Analog Brightness Control
o Gate Driver Phasing Minimizes DC Supply Current
Surges
o Per-Channel Lamp Fault Monitoring for Lamp
Open, Lamp Overcurrent, Failure to Strike, and
Overvoltage Conditions
o Accurate (±2%) On-Board Oscillator Lamp
Frequency (20kHz to 80kHz)
o Wide Range On-Board DPWM Burst-Dimming
Oscillator (22.5Hz to 440Hz)
o Can Be Synchronized to External Sources for the
Lamp and DPWM Frequencies
o < 10% to 100% Dimming Range
o Soft-Start Minimizes Audible Transformer Noise
o I2C-Compatible Serial Port and On-Board
Nonvolatile (NV) Memory Allow Device
Customization
o 3-Byte NV User Memory for Storage of Serial
Numbers and Date Codes
o 4.5V to 5.5V Single-Supply Operation
o -40°C to +85°C Temperature Range
o 28-Pin SO (300 mils) Package
Ordering Information
PART
TEMP RANGE
DS3994Z+
-40°C to +85°C
+Denotes lead-free package.
PIN-PACKAGE
28 SO-300
Typical Operating Circuits appear at end of data sheet.
______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
DataSheet4 U .com






DS3994 Datasheet, Funktion
www.DataSheet4U.com
4-Channel Cold-Cathode
Fluorescent Lamp Controller
Typical Operating Characteristics (continued)
(VCC = +5.0V, TA = +25°C, unless otherwise noted.)
BURST DIMMING AT 150Hz AND 50%
1ms
5.0V GA
1ms
5.0V GB
1ms
2.0V LCM
1ms
1.0V OVD
20µs
5.0V GA
20µs
5.0V GB
20µs
2.0V LCM
20µs
1.0V OVD
SOFT-START AT VINV = 18V
LAMP STRIKE—EXPANDED VIEW
1ms
5.0V GA
1ms
5.0V GB
1ms
2.0V LCM
1ms
2.0V OVD
LAMP STRIKE WITH OPEN LAMP
AUTORETRY DISABLED
0.55
5.0V GA
0.55
5.0V GB
0.55
2.0V LCM
0.55
1.0V OVD
LST0 AND LST1 = 0
2.0ms
5.0V GA1
2.0ms
5.0V GA2
2.0ms
5.0V GA3
2.0ms
5.0V GA4
BURST DIMMING STAGGER
LAMP OUT (LAMP OPENED),
AUTORETRY DISABLED
0.1s
5.0V GA
0.1s
5.0V GB
0.1s
2.00V LCM
0.1s
2.00V OVD
LAMP OPENED
2ms
5.0V GA
2ms
2.0V LCM
2ms
0.5V OVD
LAMP STRIKE WITH 0%
FREQUENCY BOOST
2ms
5.0V GA
2ms
2.0V LCM
2ms
0.5V OVD
LAMP STRIKE WITH 33%
FREQUENCY BOOST
6 _____________________________________________________________________
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6 Page









DS3994 pdf, datenblatt
www.DataSheet4U.com
4-Channel Cold-Cathode
Fluorescent Lamp Controller
When the DPWM signal is provided by an external
source, either from the PSYNC pin of another DS3994 or
from some other user-generated source, it is input into the
PSYNC I/O pin of the DS3994. In this mode, the BRIGHT
and POSC inputs are disabled and should be grounded
(see Figure 4). When multiple DS3994s are used in a
design, DS3994s configured to use externally generated
DPWM signals are referred to as DPWM receivers.
Burst Dimming Stagger (BDS) Functionality
The DS3994 also features burst dimming stagger (BDS)
functionality integrated into the burst dimming con-
troller. BDS is useful to reduce the current ripple on the
DC supply as well as improve the visual motion
response of the LCD panel. This feature allows users to
enter a digital code into each channel independent
register (BDS1/2/3/4) that would delay the start of each
burst period. The 8-bit BDS code can be calculated by
using Table 2 and the following equations.
Table 2. Multiplication Factor M, Based on Lamp Frequency Oscillator and DPWM
Frequency Oscillator
POSCR1
(CR2.2)
0
0
1
1
POSCR0
(CR2.1)
SELECTED PWM
OSCILLATOR RANGE (Hz)
0 22.5 to 55
1 45 to 110
0 90 to 220
1 180 to 440
M, LAMP CYCLE PERIOD MULTIPLICATION FACTOR
LAMP OSCILLATOR = 40
TO 80kHz (LOFS = 0)
LAMP OSCILLATOR = 20
TO 40kHz (LOFS = 1)
88
44
22
11
BDS_Resolution = M
fLF : OSC
BDS_Delay = BDS_Resolution x BDS_8-Bit_Value
If a BDS_Delay is used that is longer than the burst peri-
od, then the gate drivers, GA and GB, have no output.
For example, assume a lamp frequency of 50kHz and a
burst frequency of 167Hz. The step resolution of the
burst-dimming stagger would be 40µs (2/50,000). To
achieve equal stagger, as shown in Figure 5, the
BDS1/2/3/4 registers would be programmed as
described in Table 3.
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
BURST DIMMING CYCLE (167Hz/6ms)
1.5ms
3.0ms
4.5ms
Figure 5. Example Burst Dimming Stagger Cycle
Table 3. Example BDS1/2/3/4 Programmed Values
CHANNEL
1
2
3
4
REGISTER
BDS1
BDS2
BDS3
BDS4
DESIRED STAGGER (ms)
0
1.5
3.0
4.5
STEP RESOLUTION (µs)
40
40
40
40
COUNT
0
38
75
113
PROGRAMMED VALUE
00h
26h
48h
71h
12 ____________________________________________________________________
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