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PCM1808 Schematic ( PDF Datasheet ) - Burr-Brown

Teilenummer PCM1808
Beschreibung STEREO A/D CONVERTER
Hersteller Burr-Brown
Logo Burr-Brown Logo 




Gesamt 23 Seiten
PCM1808 Datasheet, Funktion
www.DataSheet4U.com
BurrĆBrown Products
from Texas Instruments
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER
FEATURES
24-Bit Delta-Sigma Stereo A/D Converter
Single-Ended Voltage Input: 3 Vp-p
High Performance:
– THD + N: –93 dB (Typical)
– SNR: 99 dB (Typical)
– Dynamic Range: 99 dB (Typical)
Oversampling Decimation Filter:
– Oversampling Frequency: ×64
– Pass-Band Ripple: ±0.05 dB
– Stop-Band Attenuation: –65 dB
– On-Chip High-Pass Filter: 0.91 Hz (48 kHz)
Flexible PCM Audio Interface
– Master/Slave Mode Selectable
– Data Formats: 24-Bit I2S, 24-Bit
Left-Justified
Power Down and Reset by Halting System
Clock
Analog Antialias LPF Included
Sampling Rate: 8 kHz–96 kHz
System Clock: 256 fS, 384 fS, 512 fS
Dual Power Supplies:
– 5-V for Analog
– 3.3-V for Digital
Package: 14-Pin TSSOP
APPLICATIONS
DVD Recorder
Digital TV
AV Amplifier/Receiver
MD Player
CD Recorder
Multitrack Receiver
Electric Musical Instrument
DESCRIPTION
The PCM1808 is high-performance, low-cost,
single-chip, stereo analog-to-digital converter with
single-ended analog voltage input. The PCM1808
uses a delta-sigma modulator with 64-times
oversampling and includes a digital decimation filter
and high-pass filter that removes the dc component
of the input signal. For various applications, the
PCM1808 supports master and slave mode and two
data formats in serial audio interface.
The PCM1808 supports the power-down and reset
function by means of halting the system clock.
The PCM1808 is suitable for wide variety of
cost-sensitive consumer applications where good
performance and operation with a 5-V analog supply
and 3.3-V digital supply is required. The PCM1808 is
fabricated using a highly advanced CMOS process
and is available in a small, 14-pin TSSOP package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated






PCM1808 Datasheet, Funktion
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
Functional Block Diagram
VINL
VREF
VINR
Antialias
LPF
Reference
Antialias
LPF
Delta-Sigma
Modulator
Delta-Sigma
Modulator
×1/64
Decimation
Filter
with
High-Pass Filter
www.ti.com
Serial
Interface
Mode/
Format
Control
BCK
LRCK
DOUT
FMT
MD1
MD0
Power Supply
Clock and Timing Control
SCKI
VCC AGND DGND VDD
B0004-10
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless
otherwise noted.
DECIMATION FILTER FREQUENCY RESPONSE
50
0
−50
−100
−150
−200
0
OVERALL CHARACTERISTICS
8 16 24
Normalized Frequency [× fS]
Figure 1.
32
G001
STOP-BAND ATTENUATION CHARACTERISTICS
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.00
0.25 0.50 0.75
Frequency [× fS]
Figure 2.
1.00
G002
6 Submit Documentation Feedback

6 Page









PCM1808 pdf, datenblatt
PCM1808
SLES177A – APRIL 2006 – REVISED AUGUST 2006
Fade-In Complete
Fade-In Start
DOUT
(Contents) BPZ
www.ti.com
Fade-Out Start
Fade-Out Complete
48/fin or 48/fS
48/fin or 48/fS
Figure 18. Fade-In and Fade-Out Operations
T0080-01
POWER ON
The PCM1808 has an internal power-on-reset circuit, and initialization (reset) is performed automatically when
the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical), and for 1024 system-clock counts
after VDD > 2.2 V (typical), the PCM1808 stays in the reset state and the digital output is forced to zero. The
digital output is valid after the reset state is released and the time of 8960/fS has elapsed. Because the fade-in
operation is performed, it takes additional time of 48/fin or 48/fS until the data corresponding to the analog input
signal is obtained. Figure 19 illustrates the power-on timing and the digital output.
2.6 V
VDD 2.2 V
1.8 V
Internal
Reset
System
Clock
DOUT
DOUT
(Contents)
BPZ
12
Reset
1024 System Clocks
Reset Release
Operation
8960/fS
Zero Data
Fade-In Start
Normal Data
Fade-In Complete
Figure 19. Power-On Timing
Submit Documentation Feedback
48/fin or 48/fS
T0014-09

12 Page





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