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AD7294 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7294
Beschreibung DAC/ADC Temperature Sensor and Current Sense
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 45 Seiten
AD7294 Datasheet, Funktion
www.DataSheet4U.com
12-Bit, Multichannel, DAC/ADC Temperature Sensor and
Current Sense for Monitor and Control Applications
Preliminary Technical Data
AD7294
FEATURES
GENERAL DESCRIPTION
4-channel 12-bit DAC
Guaranteed monotonic
10 μs settling time
10 mA sink and source capability
Offset in for range adjustment
The AD7294 contains all the functions required for general-
purpose monitoring and control of current, voltage, and
temperature integrated into a single-chip solution. The part
includes low voltage (±200 mV) analog-input sense amplifiers
Output span: 5 V in 0 to 15 V range
9-channel, 12-bit ADC
200 kSPS throughput
Input range: 0 to VREF, 0 to 2 VREF
Differential/single-ended
Limit registers per channel
for current monitoring across shunt resistors, temperature-sense
inputs, and four uncommitted analog input channels multiplexed
into a 200 kSPS SAR ADC. An internal low ppm reference is
provided to drive both the DAC and ADC. Four 12-bit DACs
provide the outputs for voltage control. The AD7294 also includes
2 high-side current sense
limit registers for alarm functions. The part is designed on a high
48 V max operation
±1% FS accuracy
±200 mV input range
voltage DMOS process for a high voltage compliance, 48 V on
the current-sense inputs, and up to 15 V DAC output voltage.
3-channel temperature sensor
Diode temperature measurement
±2°C accuracy
Measurement range: −10°C to +90°C
The part is ideal for bias current control of the power transistors
used in power amplifiers employed in CDMA, GSM, EDGE, and
UMTS cellular base stations.
Internal 2.5 V reference
I2C®-compatible serial interface
Temperature range: −40°C to +105°C
The DACs provide digital control with 1.2 mV resolution to
control the bias currents of the power transistors. They can also
Alert function
be used to provide control voltages for variable gain amplifiers
Package type: LFCSP-56, TQFP-64
or impedance match networks in the main signal chain. Thermal
APPLICATIONS
diode based temperature sensors are incorporated to compensate
for temperature effects. The ADC monitors the high-side current
Cellular base station (GSM, EDGE, UMTS, CDMA)
Point-to-multipoint and other RF transmission systems
12 V, 24 V, 48 V automotive applications
Industrial control
and temperature. All this functionality is provided in a 56-lead
LFCSP package and a 64-lead TQFP package operating over a
temperature range of −40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
R Sense
VPP(1-2)
RS1(+) RS1(-)
RS2(+) RS2(-)
REFOUT/
REFOUT/
REFIN ADC REFIN DAC AVDD(1-5) AGND(1-9) V+(1-2)
RF CHOKE
ISENSE2
OVER-RANGE
ISENSE1
OVER-RANGE
VIN 0
VIN 1
VIN 2
VIN 3
D1 (+)
HIGH SIDE
CURRENT
SENSE
SET-POINT
240mV
HIGH SIDE
CURRENT
SENSE
MUX
2.5V
REF
12-BIT
ADC
12-BIT
DAC
100K
100K 200K
200K
12-BIT
DAC
100K
100K 200K
200K
VOUT A
FILTER
OFFSET IN A
VOUT B
FILTER
RF OUT
LDMOS
LDMOS
D0 (+)
T1 T0
D0 (-)
D1 (-)
AD7294
LIMIT
REGISTERS
TEMP
SENSOR
CONTROL
LOGIC
I2C INTERFACE
PROTOCOL
12-BIT
DAC
100K
100K 200K
200K
12-BIT
DAC
100K
100K 200K
200K
OFFSET IN B
VOUT C GAIN
CONTROL
OFFSET IN C
VOUT D
IMPEDANCE
MATCH
OFFSET IN D
DVDD DGND(1-2) SDA SCL A2 A1 A0 CAP ALERT
Figure 1. Typical Configuration for AD7294 in Cellular Base Station RF LDMOS Power Amplifier Control
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






AD7294 Datasheet, Funktion
www.DataSheet4U.com
AD7294
Preliminary Technical Data
TIMING CHARACTERISTICS1,2
I2C Serial Interface
DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
FSCL
t1
t2
t3
t4
t5
t63
t7
t8
t9
t10
t11
Cb
Limit at TMIN, TMAX
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1Cb4
400
Unit
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Description
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data set-up time
tHD,DAT, data hold time
tHD,DAT, data hold time
tSU,STA, set-up time for repeated start
tSU,STO, stop condition set-up time
tBUF, bus free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
1 Guaranteed by design and characterization; not subject to production test.
2 See Figure 2.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge.
4 Cb is the total capacitance in pF of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.
SDA
t9
t3
SCL
t4
START
CONDITION
t10 t11
t4
t6 t2
t5
t7
REPEATED
START
CONDITION
Figure 2. I2C-Compatible Serial Interface Timing Diagram
t1
200µA
IOL
TO OUTPUT PIN
CL
50pF
200µA
IOH
VOH (MIN) OR
VOL (MAX)
Figure 3. Load Circuit for Digital Output
Rev. PrB | Page 6 of 45
t8
STOP
CONDITION

6 Page









AD7294 pdf, datenblatt
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AD7294
Preliminary Technical Data
ADC INFORMATION
The AD7294 consists of a successive 200 kSPS approximation
analog-to-digital converter based around a capacitive DAC. The
analog input range for the part can be selected to be a 0 V to VREF
input or a 2 × VREF input, configured with either single-ended or
differential analog inputs. The AD7294 has an on-chip 2.5 V refer-
ence that can be n when an external reference is preferred. If the
internal reference is to be used elsewhere in a system, the output
must be buffered first.
The various monitored and uncommitted input signals are multi-
plexed into the ADC. The nine channel-allocation address bits
select which analog input channel to convert using the multiplexer.
Four uncommitted analog input channels are multiplexed to the
ADC, VIN (0 to 3). These four channels allow differential and
pseudodifferential mode measurements of various system signals.
ADC OPERATION
Figure 7 shows a very simplified schematic of the ADC. The
control logic, SAR and capacitive DACs are used to add and
subtract fixed amounts of charge from the sampling capacitor
arrays to bring the comparator back to a balanced condition.
CAPACITIVE
DAC
COMPARATOR
VIN
VREF
SWITCHES
SAR
CONTROL
INPUTS
CONTROL
LOGIC
OUTPUT DATA
14-BIT PARALLEL
Figure 7. Simplified ADC Block Diagram
Figure 8 and Figure 9 show simplified schematics of the ADC
during its acquisition and conversion phases in differential mode,
respectively. Figure 8 shows the ADC during its acquisition
phase. SW3 is closed, SW1 and SW2 are in Position A, the
comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
VIN+
VIN–
B CS
A SW1
A SW2
B
CS
VREF
CAPACITIVE
DAC
COMPARATOR
SW3
CONTROL
LOGIC
CAPACITIVE
DAC
Figure 8. ADC Acquisition Phase
When the ADC starts a conversion, as shown in Figure 9, SW3
opens, and SW1 and SW2 move to Position B, causing the com-
parator to become unbalanced. Both inputs are disconnected
once the conversion begins. When the comparator is rebalanced,
the conversion is complete. The control logic generates the ADC
output code. The output impedances of the sources driving the
VIN+ and VIN− pins must be matched; otherwise, the two inputs
will have different settling times, resulting in errors.
VIN+
VIN–
B CS
A SW1
A SW2
B
CS
VREF
CAPACITIVE
DAC
COMPARATOR
SW3
CONTROL
LOGIC
CAPACITIVE
DAC
Figure 9. ADC Conversion Phase
ADC TRANSFER FUNCTIONS
The designed code transitions occur at successive integer LSB
values (1 LSB, 2 LSB, and so on). In single-ended mode, the
LSB size is VREF/4,096 when the 0 V to VREF range is used and
2 × VREF/4,096 when the 0 V to 2 × VREF range is used.
111...111
111...110
111...000
011...111
1LSB = VREF/4096
000...010
000...001
000...000
0V 1LSB
VREF – 1LSB
ANALOG INPUT
NOTE
1. VREF IS EITHER VREF OR 2 × VREF.
Figure 10. Straight Binary Transfer Characteristic
In differential mode, the LSB size is 2 × VREF /4,096 when the 0 V
to VREF range is used and 4 × VREF/4,096 when the 0 V to 2 × VREF
range is used. The ideal transfer characteristic for the ADC when
outputting straight binary coding is shown in Figure 10, and the
ideal transfer characteristic for the ADC when outputting twos
complement coding is shown in Figure 11 (this is shown with
the 2 × VREF range).
Rev. PrB | Page 12 of 45

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