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PDF AD12401 Data sheet ( Hoja de datos )
| Número de pieza | AD12401 | |
| Descripción | 400 MSPS A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Up to 400 MSPS sample rate
SNR of 63 dBFS @128 MHz
SFDR of 70 dBFS @128 MHz
VSWR of 1:1.5
High or low gain grades
Wideband ac-coupled input signal conditioning
Enhanced spurious-free dynamic range
Single-ended or differential ENCODE signal
LVDS output levels
Twos complement output data
APPLICATIONS
Communications test equipment
Radar and satellite subsystems
Phased array antennas, digital beams
Multichannel, multimode receivers
Secure communications
Wireless and wired broadband communications
Wideband carrier frequency systems
GENERAL DESCRIPTION
The AD12401 is a 12-bit analog-to-digital converter (ADC)
with a transformer-coupled analog input and digital post-
processing for enhanced SFDR. The product operates at up to
400 MSPS conversion rate with outstanding dynamic performance
in wideband carrier systems.
The AD12401 requires a 3.7 V analog supply and 3.3 V and
1.5 V digital supplies, and provides a flexible ENCODE signal
that can be differential or single ended. No external reference is
required.
The AD12401 package style is an enclosed 2.9" × 2.6" × 0.6"
module. Performance is rated over a 0°C to 60°C case
temperature range.
12-Bit, 400 MSPS A/D Converter
AD12401
FUNCTIONAL BLOCK DIAGRAM
AD12401
DATA
READY
A
ADC
A
DA0–DA11
POST-
CLK DISTRIBUTION PROCESSING
DB0–DB11
AIN
ADC
B
DR_EN
CLOCK DISTRIBUTION
DIVIDE BY 2
DATA
READY
B
ENC
ENC
OROUT
Figure 1.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate up to 400 MSPS.
2. Input signal conditioning with optimized dynamic
performance to 175 MHz.
3. High and low gain grades available.
4. Additional performance options available (sample rates
>400 MSPS or second Nyquist zone operation); contact
sales.
5. Proprietary Advanced Filter Bank (AFB™) digital post-
processing from V Corp Technologies, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
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AD12401
Parameter
DIGITAL OUTPUT PARAMETERS
Valid Time (tV)
Propagation Delay (tPD)
Rise Time, tR (20% to 80%)
Fall Time, tF (20% to 80%)
DR Propagation Delay (tEDR)
Data to DR Skew (tEDR − tPD)
Pipeline Latency7
Start-Up Time
Postprocessing Configuration Time
APERTURE DELAY (tA)
APERTURE UNCERTAINTY (Jitter, tJ)
Case Temp
Full
60°C
60°C
60°C
60°C
60°C
Full
Full
Full
60°C
60°C
Test Level
IV
V
V
V
V
V
IV
IV
IV
V
V
AD12401-400KWS
AD12401-400JWS
Min Typ Max Min Typ Max Unit
3.9
8.7
0.3
0.3
11.2
2.5
74
29 44 87
2.8
2.3
0.4
3.9
8.7
0.3
0.3
11.2
2.5
74
29 44 87
2.8
2.3
0.4
ns
ns
ns
ns
ns
ns
Cycles
ms
sec
ns
ps rms
1 All ac specifications tested with a single-ended, 2.0 V p-p encode on ENCODE and ENCODE floating.
2 The image spur is included in the SINAD measurement.
3 The image spur is not included in the SFDR specification.
4 The image spur is at fS/2 – AIN; the offset spur is at fS/2.
5 F1 = 70 MHz, F2 = 73 MHz.
6 Parts are tested with 400 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design
for encode 400 MSPS ± 1%.
7 Pipeline latency is exactly 74 cycles with an additional tPD required for data to emerge.
AC SPECIFICATIONS1—ENCODE = 360 MSPS
VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, encode = 360 MSPS, 0°C ≤ TCASE ≤ 60°C, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
SNR
Analog Input 10 MHz
@ −1.0 dBFS 70 MHz
128 MHz
SINAD2
Analog Input 10 MHz
@ −1.0 dBFS 70 MHz
128 MHz
Spurious-Free Dynamic Range3
Analog Input 10 MHz
@ −1.0 dBFS 70 MHz
128 MHz
Image Spur4
Analog Input 10 MHz
@ −1.0 dBFS 70 MHz
128 MHz
Offset Spur4
Analog Input @ −1.0 dBFS
Two-Tone IMD5
F1, F2 @ −6 dBFS
ANALOG INPUT
Frequency Range
DIGITAL INPUT (DR_EN)
Minimum Time (Low)
Case Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
60°C
60°C
Full
Full
Test Level
I
I
I
I
I
I
I
I
I
I
I
I
V
V
IV
IV
AD12401-360KWS
Min Typ Max
62 64
61.5 63.5
60 63
59 63.5
58.5 63
57.5 61.5
69 85
69 80
66 72
60 75
60 72
60 66
65
−75
10 160
5.6
Rev. A | Page 5 of 28
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
MHz
ns
5 Page 
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AD12401
Table 9. Pin Function Descriptions
Pin No.
Mnemonic Description
1 to 4
VC Digital Supply, 3.3 V.
5
RESET
LVTTL. 0 = device reset. Minimum width = 200 ns. Device resumes operation after 600 ms maximum.
6 to 9, 11, 13 ,15,
49 to 52, 79, 96 to
102, 104 to108
DNC
Do Not Connect.
10 DRB Channel B Data Ready. Complement output.
12 DRB Channel B Data Ready. True output.
14
OROUT
Overrange. Complement output.
16
OROUT
Overrange. True Output 1 = overranged, 0 = normal operation.
17
DB11
Channel B Data Bit 11. Complement output bit.
18
DB10
Channel B Data Bit 10. Complement output bit.
19
DB11
Channel B Data Bit 11. True output bit.
20
DB10
Channel B Data Bit 10. True output bit.
21 DB9 Channel B Data Bit 9. Complement output bit.
22 DB8 Channel B Data Bit 8. Complement output bit.
23 DB9 Channel B Data Bit 9. True output bit.
24 DB8 Channel B Data Bit 8. True output bit.
25 DB7 Channel B Data Bit 7. Complement output bit.
26 DB6 Channel B Data Bit 6. Complement output bit.
27 DB7 Channel B Data Bit 7. True output bit.
28 DB6 Channel B Data Bit 6. True output bit.
29 DB5 Channel B Data Bit 5. Complement output bit.
30 DB4 Channel B Data Bit 4. Complement output bit.
31 DB5 Channel B Data Bit 5. True output bit.
32 DB4 Channel B Data Bit 4. True output bit.
33 DB3 Channel B Data Bit 3. Complement output bit.
34 DB2 Channel B Data Bit 2. Complement output bit.
35 DB3 Channel B Data Bit 3. True output bit.
36 DB2 Channel B Data Bit 2. True output bit.
37 DB1 Channel B Data Bit 1. Complement output bit.
38 DB0 Channel B Data Bit 0. Complement output bit. DB0 is LSB.
39 DB1 Channel B Data Bit 1. True output bit.
40 DB0 Channel B Data Bit 0. True output bit. DB0 is LSB.
41 to 48
VD Digital Supply, 1.5 V.
53
DA11
Channel A Data Bit 11. Complement output bit.
54
DA10
Channel A Data Bit 10. Complement output bit.
55
DA11
Channel A Data Bit 11. True output bit.
56
DA10
Channel A Data Bit 10. True output bit.
57 DA9 Channel A Data Bit 9. Complement output bit.
58 DA8 Channel A Data Bit 8. Complement output bit.
59 DA9 Channel A Data Bit 9. True output bit.
60 DA8 Channel A Data Bit 8. True output bit.
61 DA7 Channel A Data Bit 7. Complement output bit.
62 DA6 Channel A Data Bit 6. Complement output bit.
63 DA7 Channel A Data Bit 7. True output bit.
64 DA6 Channel A Data Bit 6. True output bit.
65 DA5 Channel A Data Bit 5. Complement output bit.
66 DA4 Channel A Data Bit 4. Complement output bit.
67 DA5 Channel A Data Bit 5. True output bit.
68 DA4 Channel A Data Bit 4. True output bit.
Rev. A | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD12401.PDF ] | |
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