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PDF ADF4156 Data sheet ( Hoja de datos )
| Número de pieza | ADF4156 | |
| Descripción | 6.2 GHz Fractional-N Frequency Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
6.2 GHz Fractional-N Frequency Synthesizer
ADF4156
FEATURES
RF bandwidth to 6.2 GHz
2.7 V to 3.3 V power supply
Separate VP pin allows extended tuning voltage
Programmable fractional modulus
Programmable charge-pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with ADF4110/ADF4111/ADF4112/ADF4113,
ADF4106, ADF4153, and ADF4154 frequency synthesizers
Programmable RF output phase
Loop filter design possible with ADIsimPLL
Cycle slip reduction for faster lock times
APPLICATIONS
CATV equipment
Base stations for mobile radio (WiMAX, GSM, PCS, DCS,
SuperCell 3G, CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs, PMR
Communications test equipment
GENERAL DESCRIPTION
The ADF4156 is a 6.2 GHz fractional-N frequency synthesizer
that implements local oscillators in the upconversion and down-
conversion sections of wireless receivers and transmitters. It
consists of a low noise digital phase frequency detector (PFD), a
precision charge pump, and a programmable reference divider.
There is a Σ-Δ based fractional interpolator to allow programmable
fractional-N division. The INT, FRAC, and MOD registers define
an overall N divider (N = (INT + (FRAC/MOD))). The RF output
phase is programmable for applications that require a particular
phase relationship between the output and the reference. The
ADF4156 also features cycle slip reduction circuitry, leading
to faster lock times without the need for modifications to the
loop filter.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
ADF4156
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP
RSET
REFIN
MUXOUT
CE
×2
DOUBLER
5-BIT
R-COUNTER
/2
DIVIDER
HIGH Z
OUTPUT
MUX
VDD
DGND
SDOUT
VDD
RDIV
NDIV
LOCK
DETECT
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
REFERENCE
+ PHASE
FREQUENCY
DETECTOR
–
CHARGE
PUMP
CURRENT
SETTING
CSR
CP
RFCP4 RFCP3 RFCP2 RFCP1
N-COUNTER
RFINA
RFINB
CLOCK
DATA
LE
32-BIT
DATA
REGISTER
FRACTION MODULUS
REG
REG
INTEGER
REG
AGND
DGND
Figure 1.
CPGND
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADF4156
Data Sheet
TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit at TMIN to TMAX (B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
Timing Diagram
CLOCK
DATA
DB23 (MSB)
LE
t1
LE
t2 t3
DB22
t4 t5
DB2
DB1
(CONTROL BIT C2)
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. E | Page 4 of 24
5 Page 
ADF4156
Data Sheet
REGISTER MAPS
FRAC/INT REGISTER (R0)
RE-
SERVED
MUXOUT CONTROL
12-BIT INTEGER VALUE (INT)
12-BIT FRACTIONAL VALUE (FRAC)
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(0)
PHASE REGISTER (R1)
RESERVED
12-BIT PHASE VALUE (PHASE)1
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C3(0) C2(0) C1(1)
MOD/R REGISTER (R2)
NOISE
MODE
CURRENT
SETTING1
5-BIT R COUNTER1
12-BIT MODULUS WORD1
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 L2 L1 C1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 U1 R5 R4 R3 R2 R1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(1) C1(0)
FUNCTION REGISTER (R3)
RESERVED
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U12 0 0 0 0 0 0 U7 U6 U5 U4 U3 C3(0) C2(1) C1(1)
CLK DIV REGISTER (R4)
RESERVED
CLK
DIV
MODE
12-BIT CLOCK DIVIDER VALUE
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 M2 M1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 C3(1) C2(0) C1(0)
1DOUBLE BUFFERED BIT.
Figure 16. Register Summary
Rev. E | Page 10 of 24
11 Page | ||
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| PDF Descargar | [ Datasheet ADF4156.PDF ] | |
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