|
|
PDF AD9212 Data sheet ( Hoja de datos )
| Número de pieza | AD9212 | |
| Descripción | Serial LVDS A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9212 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
Octal, 10-Bit, 40 MSPS/65 MSPS,
Serial LVDS, 1.8 V ADC
AD9212
FEATURES
8 analog-to-digital converters (ADCs) integrated into 1 package
100 mW ADC power per channel at 65 MSPS
SNR = 60.8 dB (to Nyquist)
ENOB = 9.8 bits
SFDR = 80 dBc (to Nyquist)
Excellent linearity
DNL = ±0.3 LSB (typical); INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
325 MHz, full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9212 is an octal, 10-bit, 40 MSPS/65 MSPS ADC with an
on-chip sample-and-hold circuit designed for low cost, low power,
small size, and ease of use. Operating at a conversion rate of up to
65 MSPS, it is optimized for outstanding dynamic performance
and low power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO)
for capturing data on the output and a frame clock (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD DRGND
VIN + A
VIN – A
VIN + B
VIN – B
VIN + C
VIN – C
VIN + D
VIN – D
VIN + E
VIN – E
VIN + F
VIN – F
VIN + G
VIN – G
VIN + H
VIN – H
VREF
SENSE
REFT
REFB
AD9212
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
REF
SELECT
0.5V
SERIAL PORT
INTERFACE
10
SERIAL
LVDS
10
SERIAL
LVDS
10
SERIAL
LVDS
10
SERIAL
LVDS
10
SERIAL
LVDS
10
SERIAL
LVDS
10
SERIAL
LVDS
10
SERIAL
LVDS
DATA RATE
MULTIPLIER
D+A
D–A
D+B
D–B
D+C
D–C
D+D
D–D
D+E
D–E
D+F
D–F
D+G
D–G
D+H
D–H
FCO+
FCO–
DCO+
DCO–
RBIAS AGND CSB
SDIO/ SCLK/
ODM DTP
Figure 1.
CLK+
CLK–
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9212 is available in a RoHS-compliant, 64-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight ADCs are contained in a small package.
2. Low Power of 100 mW per Channel at 65 MSPS.
3. Ease of Use. A data clock output (DCO) operates up to
300 MHz and supports double data rate (DDR) operation.
4. User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9222 (12-bit)
and AD9252 (14-bit).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.
1 page  
AD9212
Data Sheet
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1.
Parameter1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Voltage (1 V Mode)
REFERENCE
Output Voltage Error (VREF = 1 V)
Load Regulation @ 1.0 mA (VREF = 1 V)
Input Resistance
ANALOG INPUTS
Differential Input Voltage Range (VREF = 1 V)
Common-Mode Voltage
Differential Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
AVDD
DRVDD
IAVDD
IDRVDD
Total Power Dissipation (Including Output Drivers)
Power-Down Dissipation
Standby Dissipation2
CROSSTALK
AIN = −0.5 dBFS
Overrange3
Temperature
AD9212-40
Min Typ
Max
10
AD9212-65
Min Typ
Max
10
Unit
Bits
Full
Guaranteed
Guaranteed
Full
±1.5 ±8
±1.5 ±8 mV
Full
±3 ±8
±3 ±8 mV
Full
±0.4 ±1.2
±3.2 ±4.3 % FS
Full
±0.3 ±0.7
±0.4 ±0.9 % FS
Full
±0.1 ±0.4
±0.3 ±0.65 LSB
Full
±0.15 ±0.5
±0.4 ±1 LSB
Full ±2
Full ±17
Full ±21
±2 ppm/°C
±17 ppm/°C
±21 ppm/°C
Full
±2 ±30
±2 ±30 mV
Full 3
3 mV
Full 6
6 kΩ
Full 2
2 V p-p
Full
AVDD/2
AVDD/2
V
Full 7
7 pF
Full 325
325 MHz
Full
1.7 1.8
1.9 1.7 1.8
1.9 V
Full
1.7 1.8
1.9 1.7 1.8
1.9 V
Full
252 260
390 405 mA
Full
49.5 53
54 58 mA
Full
542 560
800 833 mW
Full
3 11
3 11 mW
Full 83
95 mW
Full −90
Full −90
−90 dB
−90 dB
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 Can be controlled via the SPI.
3 Overrange condition is specific with 6 dB of the full-scale input range.
Rev. E | Page 4 of 56
5 Page 
AD9212
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
ELECTRICAL
AVDD
DRVDD
AGND
AVDD
Digital Outputs
(D + x, D − x, DCO+,
DCO−, FCO+, FCO−)
CLK+, CLK−
VIN + x, VIN − x
SDIO/ODM
PDWN, SCLK/DTP, CSB
REFT, REFB, RBIAS
VREF, SENSE
ENVIRONMENTAL
Operating Temperature
Range (Ambient)
Storage Temperature
Range (Ambient)
Maximum Junction
Temperature
Lead Temperature
(Soldering, 10 sec)
With
Respect To Rating
AGND
DRGND
DRGND
DRVDD
DRGND
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +0.3 V
−2.0 V to +2.0 V
−0.3 V to +2.0 V
AGND
AGND
AGND
AGND
AGND
AGND
−0.3 V to +3.9 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−40°C to +85°C
−65°C to +150°C
150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Data Sheet
THERMAL IMPEDANCE
Table 6.
Air Flow Velocity (m/s)
0.0
1.0
2.5
θJA1 θJB θJC Unit
17.7 °C/W
15.5 8.7 0.6 °C/W
13.9 °C/W
1 θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad
soldered to PCB.
ESD CAUTION
Rev. E | Page 10 of 56
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9212.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9211 | 1.8 V Analog-to-Digital Converter | Analog Devices |
| AD9212 | Serial LVDS A/D Converter | Analog Devices |
| AD9214 | 3V A/D Converter | Analog Devices |
| AD9215 | 3V A/D Converter | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |