|
|
PDF DS33R41 Data sheet ( Hoja de datos )
| Número de pieza | DS33R41 | |
| Descripción | Inverse-Multiplexing Ethernet Mapper | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS33R41 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
DS33R41
Inverse-Multiplexing Ethernet Mapper with
Quad Integrated T1/E1/J1 Transceivers
www.maxim-ic.com
GENERAL DESCRIPTION
The DS33R41 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over four interleaved
T1/E1/J1 lines using a robust, balanced, and
programmable inverse multiplexing. Four integrated
T1/E1/J1 transceivers provide framing and line
interfacing functionality.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
committed information rate (CIR) controller provides
fractional bandwidth allocation up to the line rate in
increments of 512kbps.
FUNCTIONAL DIAGRAM
4 INTERLEAVED
SERIAL STREAMS
DS33R41
4 T1/E1/J1
TRANSCEIVERS
WITH BERTs
T1/E1
LINES
FEATURES
10/100 IEEE 802.3 Ethernet MAC (MII and
RMII) Half/Full Duplex with Automatic Flow
Control
Layer 1 Inverse Multiplexing Over Four
T1/E1/J1 Lines Through the Integrated
Framers and LIUs
Supports Up to 7.75ms Differential Delay
Aggregate Bandwidth from Up to Four
T1/E1/J1 Links
T1/E1 Signaling Capability for OAM
HDLC/LAPS Encapsulation with
Programmable FCS, Interframe Fill
CIR Controller Provides Fractional
Allocations in 512kbps Increments
Programmable BERTs
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
1.8V, 3.3V Power Supplies
IEEE 1149.1 JTAG Support
Features continued on page 12.
HDLC/X.86
ETHERNET
MAPPER
10/100
MAC
MII/RMII
µC
SDRAM
10/100
ETHERNET
PHY
APPLICATIONS
Bonded Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS33R41
-40°C to +85°C 400 BGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 333
REV: 102105
1 page  
www.DataSheet4U.com
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
10.17.4 FIFO Information .................................................................................................................................96
10.17.5 Receive Packet-Bytes Available .........................................................................................................96
10.18LEGACY FDL SUPPORT (T1 MODE) ............................................................................................. 97
10.18.1 Overview .............................................................................................................................................97
10.18.2 Receive Section ..................................................................................................................................97
10.18.3 Transmit Section .................................................................................................................................98
10.19D4/SLC-96 OPERATION.............................................................................................................. 98
10.20LINE INTERFACE UNIT (LIU)......................................................................................................... 99
10.20.1 LIU Operation......................................................................................................................................99
10.20.2 Receiver ..............................................................................................................................................99
10.20.3 Transmitter ........................................................................................................................................101
10.21MCLK PRESCALER ................................................................................................................... 102
10.22JITTER ATTENUATOR................................................................................................................. 102
10.23CMI (CODE MARK INVERSION) OPTION...................................................................................... 102
10.24RECOMMENDED CIRCUITS ......................................................................................................... 103
10.25T1/E1/J1 TRANSCEIVER BERT FUNCTION................................................................................. 108
10.25.1 BERT Status .....................................................................................................................................108
10.25.2 BERT Mapping..................................................................................................................................108
10.25.3 BERT Repetitive Pattern Set ............................................................................................................110
10.25.4 BERT Bit Counter..............................................................................................................................110
10.25.5 BERT Error Counter..........................................................................................................................110
10.25.6 BERT Alternating Word-Count Rate .................................................................................................110
10.26PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY) ......................................................... 111
10.26.1 Number-of-Errors Registers..............................................................................................................111
10.26.2 Number of Errors Left Register .........................................................................................................111
11 INTERLEAVED PCM BUS OPERATION..................................................................................... 112
11.1 CHANNEL INTERLEAVE MODE .................................................................................................... 112
11.2 PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER................................................................... 114
11.3 FRACTIONAL T1/E1 SUPPORT ................................................................................................... 114
11.4 T1/E1/J1 TRANSMIT FLOW DIAGRAMS....................................................................................... 115
12 DEVICE REGISTERS................................................................................................................... 119
12.1 REGISTER BIT MAPS ................................................................................................................. 120
12.1.1 Global Register Bit Map ....................................................................................................................120
12.1.2 Arbiter Register Bit Map....................................................................................................................121
12.1.3 Serial Interface Register Bit Map ......................................................................................................122
12.1.4 Ethernet Interface Register Bit Map..................................................................................................124
12.1.5 MAC Register Bit Map ......................................................................................................................125
12.2 T1/E1/J1 TRANSCEIVER REGISTER BIT MAP.............................................................................. 127
12.3 GLOBAL REGISTER DEFINITIONS FOR ETHERNET MAPPER .......................................................... 132
12.4 ARBITER REGISTERS ................................................................................................................. 144
12.4.1 Arbiter Register Bit Descriptions .......................................................................................................144
12.5 SERIAL INTERFACE REGISTERS.................................................................................................. 145
12.5.1 Serial Interface Transmit and Common Registers............................................................................145
12.5.2 Serial Interface Transmit Register Bit Descriptions ..........................................................................145
12.5.3 Transmit HDLC Processor Registers................................................................................................146
12.5.4 X.86 Registers...................................................................................................................................152
12.5.5 Receive Serial Interface....................................................................................................................154
12.6 ETHERNET INTERFACE REGISTERS ............................................................................................ 167
12.6.1 Ethernet Interface Register Bit Descriptions.....................................................................................167
12.6.2 MAC Registers ..................................................................................................................................178
12.7 TRANSCEIVER REGISTERS......................................................................................................... 194
12.7.1 Number-of-Errors Left Register.........................................................................................................292
13 FUNCTIONAL TIMING ................................................................................................................. 293
13.1 MII AND RMII INTERFACES ........................................................................................................ 293
5 of 333
5 Page 
www.DataSheet4U.com
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
An 8-bit parallel microcontroller port provides access for control and configuration of all the features of the device.
The internal 100MHz SDRAM controller interfaces to a 32-bit wide 128Mbit SDRAM. The SDRAM is used to buffer
the data from the Ethernet and WAN ports for transport. The external SDRAM can accommodate up to 8192
frames with a maximum frame size of 2016 bytes. Diagnostic capabilities include SDRAM BIST, loopbacks, PRBS
pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection. The DS33R41
operates with a 1.8V core supply and 3.3V I/O supply.
The integrated Ethernet mapper is software compatible with the DS33Z41 quad inverse-multiplexing Ethernet
mapper. There are a few things to note when porting a DS33Z41 application to this device:
• RSER has been renamed to RSERI.
• RCLK has been renamed to RCLKI.
• TSER has been renamed to TSERO.
• TCLK has been renamed to TCLKE.
The integrated T1/E1/J1 transceivers are software compatible with the DS21458 quad T1/E1/J1 transceiver. There
are a few things to note when porting a DS21458 application to this device:
• The facilities data link (FDL) support is available through software only. The TLINK, RLINK, TLCLK,
RLCLK pins are not available on the DS33R41.
• Multiplexed microprocessor bus mode is not supported on the DS33R41.
• The extended system information bus (ESIB) is not supported on the DS33R41.
• The RSIGF signaling freeze indication hardware pin is not available.
• The user output pins UOP1, UOP2, UOP3, and UOP4 are not available.
11 of 333
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS33R41.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS33R41 | Inverse-Multiplexing Ethernet Mapper | Maxim Integrated Products |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |