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ADV7321 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7321
Beschreibung (ADV7320 / ADV7321) Multiformat 216 MHz Video Encoder
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADV7321 Datasheet, Funktion
Multiformat 216 MHz
Video Encoder with Six NSV® 12-Bit DACs
ADV7320/ADV7321
FEATURES
High definition (HD) input formats
16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb
Fully compliant with
SMPTE 274M (1080i, 1080p @ 74.25 MHz)
SMPTE 296M (720p)
SMPTE 240M (1035i)
RGB in 3-bit × 10-bit 4:4:4 input format
HDTV RGB supported
RGB, RGBHV
Other HD formats using async timing mode
Enhanced definition (ED) input formats
8-/10-, 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb
SMPTE 293M (525p)
BTA T-1004 EDTV2 (525p)
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
RGB in 3-bit × 10-bit 4:4:4 input format
Standard definition (SD) input formats
CCIR-656 4:2:2 8-/10-bit or 16-/20-bit parallel input
HD output formats
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
ED output formats
Macrovision® Rev 1.2 (525p/625p) (ADV7320 only)
CGMS-A (525p/625p)
YPrPb progressive scan (PS) (EIA-770.1, EIA-770.2)
RGB, RGBHV
SD output formats
Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC-compatible composite video
ITU-R BT.470 PAL-compatible composite video
S-video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1 (ADV7320 only)
CGMS/WSS
Closed captioning
GENERAL FEATURES
Simultaneous SD/HD or PS/SD inputs and outputs
Oversampling up to 216 MHz
Programmable DAC gain control
Sync outputs in all modes
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
On-board voltage reference
Six 12-bit NSV (noise shaped video) precision video DACs
2-wire serial I2C® interface, open-drain configuration
Dual I/O supply 2.5 V/3.3 V operation
Analog and digital supply 2.5 V
On-board PLL
64-lead LQFP package
Lead (Pb) free product
APPLICATIONS
EVD (enhanced versatile disk) players
High-end SD/PS DVD recorders/players
SD/PS/HDTV display devices
SD/HDTV set top boxes
Professional video systems
FUNCTIONAL BLOCK DIAGRAM
Y9–Y0
C9–C0
S9–S0
HSYNC
VSYNC
BLANK
CLKIN_A
CLKIN_B
STANDARD DEFINITION
CONTROL BLOCK
COLOR CONTROL
BRIGHTNESS
DNR
GAMMA
PROGRAMMABLE
FILTERS
SD TEST PATTERN
D
E PROGRAMMABLE
M RGB MATRIX
U
X
TIMING
GENERATOR
HIGH DEFINITION
CONTROL BLOCK
HD TEST PATTERN
COLOR CONTROL
ADAPTIVE FILTER CTRL
SHARPNESS FILTER
PLL
ADV7320/
ADV7321
12-BIT
DAC
O 12-BIT
V DAC
E
R
S
A
12-BIT
DAC
M
P 12-BIT
L DAC
I
N 12-BIT
G DAC
12-BIT
DAC
I2C
INTERFACE
Figure 1.
GENERAL DESCRIPTION
The ADV®7320/ADV7321 are high speed, digital-to-analog
encoders on single monolithic chips. They include six high
speed NSV video DACs with TTL-compatible inputs. They have
separate 8-/10-, 16-/20-, and 24-/30-bit input ports that accept
data in high definition (HD) and/or standard definition (SD)
video format. For all standards, external horizontal, vertical,
and blanking signals, or EAV/SAV timing codes, control the
insertion of appropriate synchronization signals into the digital
data stream and, therefore, the output signal.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






ADV7321 Datasheet, Funktion
ADV7320/ADV7321
SPECIFICATIONS
VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V, RSET = 3040 Ω, RLOAD = 300 Ω. All
specifications TMIN to TMAX (0°C to 70°C), unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE1
Resolution
Integral Nonlinearity
Differential Nonlinearity,2 +ve
Differential Nonlinearity,2 −ve
DIGITAL OUTPUTS
Output Low Voltage, VOL
Output High Voltage, VOH
Three-State Leakage Current
Three-State Output Capacitance
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current
Input Capacitance, CIN
ANALOG OUTPUTS
Full-Scale Output Current
Output Current Range
DAC-to-DAC Matching
Output Compliance Range, VOC
Output Capacitance, COUT
VOLTAGE REFERENCE
Internal Reference Range, VREF
External Reference Range, VREF
VREF Current4
POWER REQUIREMENTS
Normal Power Mode
IDD 5
Min
2.4 [2.0]3
2
4.1
4.1
0
1.15
1.15
IDD_IO
IAA7, 8
Sleep Mode
IDD
IAA
IDD_IO
POWER SUPPLY REJECTION RATIO
Typ
12
1.5
0.25
1.5
±1.0
2
10
2
4.33
4.33
1.0
1.0
7
1.235
1.235
±10
137
78
73
140
1.0
37
80
7
250
0.01
Max
0.4 [0.4]3
0.8
4.6
4.6
1.4
1.3
1.3
1906
45
Unit
Bits
LSB
LSB
LSB
V
V
μA
pF
V
V
μA
pF
mA
mA
%
V
pF
V
V
μA
mA
mA
mA
mA
mA
mA
μA
μA
μA
%/%
Test Conditions
ISINK = 3.2 mA
ISOURCE = 400 μA
VIN = 0.4 V, 2.4 V
VIN = 2.4 V
SD only (16×)
PS only (8×)
HDTV only (2×)
SD (16×, 10 bit) + PS (8×, 20 bit)
1 Oversampling disabled. Static DAC performance improves with increased oversampling ratios.
2 DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for −ve DNL, the
actual step value lies below the ideal step value.
3 For values in brackets, VDD_IO = 2.375 V to 2.75 V.
4 External current required to overdrive internal VREF.
5 IDD, the circuit current, is the continuous current required to drive the digital core.
6 Guaranteed maximum by characterization.
7 All DACs on.
8 IAA is the total current required to supply all DACs, including the VREF circuitry and the PLL circuitry.
Rev. A | Page 6 of 88

6 Page









ADV7321 pdf, datenblatt
ADV7320/ADV7321
CLKIN_B
CONTROL
INPUTS
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
C9–C0
t9 t10
t12
Y0 Y1 Y2 Y3 Y4 Y5
Cb0 Cr0 Cb2 Cr2 Cb4 Cr4
t11
HD INPUT
CLKIN_A
CONTROL
INPUTS
S_HSYNC,
S_VSYNC,
S_BLANK
t9 t10
t12
SD INPUT
S9–S0
Cb0 Y0 Cr0 Y1 Cb1 Y2
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
t11
Figure 10. HD 4:2:2 and SD 10-Bit Simultaneous Input Mode (Input Mode 101: SD Oversampled) (Input Mode 110: HD Oversampled)
CLKIN_B
CONTROL
INPUTS
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
C9–C0
t9 t10
t12
Y0 Y1 Y2 Y3 Y4 Y5
Cb0 Cr0 Cb2 Cr2 Cb4 Cr4
t11
CLKIN_A
CONTROL
INPUTS
S_HSYNC,
S_VSYNC,
S_BLANK
t9 t10
t12
S9–S0
Cb0 Y0 Cr0 Y1 Cb1 Y2
t11
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
Figure 11. PS 4:2:2 and SD 10-Bit Simultaneous Input Mode (Input Mode 011)
PS INPUT
SD INPUT
Rev. A | Page 12 of 88

12 Page





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