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ADC82124 Schematic ( PDF Datasheet ) - ETC

Teilenummer ADC82124
Beschreibung 24 Ports 10/100 Fast Ethernet Switch Controller
Hersteller ETC
Logo ETC Logo 




Gesamt 48 Seiten
ADC82124 Datasheet, Funktion
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Advanced
Communication
Devices
Data Sheet: ACD82124
24 Ports 10/100 Fast Ethernet Switch Controller
Rev.1.1.1.F
Last Update: November 5, 1998
Subject to Change
Please check ACD’s website for
update information before starting a design
Web site: http://www.acdcorp.com
or Contact ACD at:
Tel: 408-433-9898x115
Fax: 408-545-0930
ACD Confidential Material
For ACD authorized customer use only. No reproduction or redistribution without ACD’s prior permission.
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ADC82124 Datasheet, Funktion
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A port’s MAC address register is cleared on power-
up, hardware reset, or when the port enters into Link
Fail state. If the SA aging option is enabled (Register-
16 bit 4), the learned SA will be cleared if it does not
reappear within five minutes.
During the receive process, the Lookup Engine will
attempt to match the destination address with the ad-
dresses stored in the address table. If a match is found,
a link between the source port and the destination port
is established. If an external ARL is used, the ACD82124
indicates the presence of a 48-bit DA through the sta-
tus line of the ARL interface. The external ARL will use
the value of DA for address comparison and return a
result of the lookup to the ACD82124.
Frame Data
Frame data are transparent to the ACD82124. The
ACD82124 will forward the data to the destination
port(s) without interpreting the content of the frame
data field.
FCS Calculation
Each port of the ACD82124 has CRC checking logic
to verify if the received frame has a correct FCS value.
A wrong FCS value is an indication of a fragmented
frame or a frame with frame bit error. The method of
calculating the CRC value is using the following poly-
nomial,
G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11
+ x10 + x8 + x7 + x5 + x4 + x2 + x + 1
as a divider to divide the bit sequence of the incoming
frame, beginning with the first bit of the destination
address field, to the end of the data field. The result of
the calculation, which is the residue after the polyno-
mial division, is the value of the frame check sequence.
This value should be equal to the FCS field appended
at the end of the frame. If the value does not match the
FCS field of the frame, the Frame Bit Error LED of the
port will be turned on once and the packet will be
dropped.
Frame Length
During the receiving process, the MAC will monitor the
length of the received frame. Legal Ethernet frames
should have a length of not less than 64 bytes and no
more than 1518 bytes. If the carrier sense signal of a
frame is asserted for less than 76 BT, the frame is
flagged with short event error. If the length of a frame
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is less then 64 bytes, the frame is flagged with runt
error.
In order to support an application where extra byte
length is required, an Extra-Long-Frame option is pro-
vided. When the Extra long frame option is enabled
(Table 12: CFG7), only frames longer than 1530 bytes
are marked with a long event error. Frame length is
measured from the first byte of DA to the last byte of
FCS.
Frame Filtering
Frames with any kind of error will be filtered. Types of
error include code error (indicated by assertion of
RXER signal), FCS error, alignment error, short event,
runt, and long event.
Any frame heading to its own source port will be fil-
tered. If external ARL is used, the ACD82124 will filter
the frame as directed by the external ARL.
If the Spanning Tree Support option is enabled, frames
containing DA equal to any reserved Bridge Manage-
ment Group Address specified in Table 3.5 of IEEE
802.1d will not be forwarded to any ports, except the
Port-23, which may receive BPDU frames. If span-
ning tree support is not enabled, frames with DA equal
to the reserved Group Address for PBDU will be broad-
casted to all ports in the same VLAN of the source
port.
Jabber Lockup Protection
If a receiving port is active continuously for more than
50,000 BT, the port is considered to be jabbering. A
jabbering port will automatically be partitioned from the
switch system in order to prevent it from impairing the
performance of the network. The partitioned port will
be re-activated as soon as the offending signal dis-
continues.
Excessive Collision
In the event that there are more than 16 consecutive
collision, the ACD82124 will reset the counter to zero
and retransmit the packet. This implementation insures
there is no packet loss even under channel capture
situation. However, ACD82124 has an option to drop
the packet on excessive collision. When this option is
enabled (Table 12: CG11), the frame will be dropped
after 16 consecutive collisions.
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Prior to any transaction, the ACD82124 will output
thirty-two bits of ‘1’ as a preamble signal. After the
preamble, a ‘01’ signal is used to indicate the start of
the frame.
For a write operation, the device will send a ‘01’ to
signal a write operation. Following the ‘01’ write signal
will be the 5 bit ID address of the PHY device and the
5 bit register address. A ‘10’ turn around signal is then
followed. After the turn around, the 16 bit of data will
be written into the register. After the completion of the
write transaction, the line will be left in a high imped-
ance state.
For a read operation, the ACD82124 will output a ‘10’
to indicate read operation after the start of frame indi-
cator. Following the ‘10’ read signal will be the 5-bit ID
address of the PHY device and the 5-bit register ad-
dress. Then, the ACD82124 will cease driving the MDIO
line, and wait for one BT. During this time, the MDIO
should be in a high impedance state. The ACD82124
will then synchronize with the next bit of ‘0’ driven by
the PHY device, and continue on to read 16 bits of
data from the PHY device.
The system designer should set the ID of the PHY
devices as ‘1’ for port-0, ‘2’ for port-1, … and ‘24’ for
port-23. The detail timing requirement on PHY man-
agement signals are described in the chapter of “Tim-
ing Description.”
CPU Interface
The ACD82124 includes a CPU interface to enable an
external CPU to access the internal registers of the
ACD82124. The protocol used in the CPU is the asyn-
chronous serial signal (UART). The baud rate can be
from 1200 bps to 76800 bps. The ACD82124 auto-
matically detects the baud rate for each command,
and returns the result at the same baud rate. The sig-
nals in CPU interface are described in Table-6.5.
Table-6.5: CPU Interface Signals
Name
Type
Description
CPUDI
I CPU data input
CPUDO
O CPU data output
CPUIRQ
O CPU interrupt request
A command sent by CPU comes through the CPUDI
line. The command consists of 9 octets. Command
frames transmitted on CPUDI have the following for-
mat (Table-6.6):
Table-6.6: CPU Command Format
Operation Command Register Index Data Checksum
Write 0010XX11 8-bit 8-bit 24-bit 8-bit
Read 0010XX01 8-bit 8-bit 24-bit 8-bit
The byte order of data in all fields follows the big-endian
convention, i.e. most significant octet first. The bit or-
der is least significant order first. The Command octet
specifies the type of the operation. Bit 2 and bit 3 of
the command octet is used to specify the device ID of
the chip. They are set by bit 16 and bit 17 of the Reg-
ister 25 at power on strobing. The address octet speci-
fies the type of the register. The index octet specifies
the ID of the register in a register array. For write
operation, the Data field is a 4-octet value to specify
what to write into the register. For read operation, the
Data field is a 4-octet 0 as padded data. The checksum
value is an 8-bit value of exclusive-OR of all octets in
the frame, starting from the Command octet.
The ACD82124 will respond to each valid command
received by sending a response frame through the
CPUDO line. The response frames have the following
format (Table-6.7):
Table-6.7: Response Format
Response Command Result
Write
00100011 8-bit
Read
00100001 8-bit
Data
24-bit
24-bit
Checksum
8-bit
8-bit
The command octet specifies the type of the response.
The result octet specifies the result of the execution.
The Result field in a response frame is defined as:
00 for no error
01 for Checksum
10 for address incorrect
11 for MDIO waiting time-out
For response to a read operation, the Data field is a 3-
octet value to indicate the content of the register. For
response to a write operation, the Data field is 24 bits
of 0. The checksum value is an 8-bit value of exclu-
sive-OR of all octets in the response frame, starting
from the Command octet.
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