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ADF4002 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF4002
Beschreibung Phase Detector/Frequency Synthesizer
Hersteller Analog Devices
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Gesamt 21 Seiten
ADF4002 Datasheet, Funktion
Data Sheet
Phase Detector/Frequency Synthesizer
ADF4002
FEATURES
400 MHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended
tuning voltage in 3 V systems
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
104 MHz phase detector
APPLICATIONS
Clock conditioning
Clock generation
IF LO generation
GENERAL DESCRIPTION
The ADF4002 frequency synthesizer is used to implement local
oscillators in the upconversion and downconversion sections of
wireless receivers and transmitters. It consists of a low noise
digital phase frequency detector (PFD), a precision charge
pump, a programmable reference divider, and programmable
N divider. The 14-bit reference counter (R counter) allows
selectable REFIN frequencies at the PFD input. A complete
phase-locked loop (PLL) can be implemented if the synthesizer
is used with an external loop filter and voltage controlled
oscillator (VCO). In addition, by programming R and N to 1,
the device can be used as a standalone PFD and charge pump.
REFIN
CLK
DATA
LE
RFINA
RFINB
AVDD DVDD
24-BIT INPUT
REGISTER 22
SDOUT
FUNCTIONAL BLOCK DIAGRAM
VP CPGND
REFERENCE
RSET
14-BIT
R COUNTER
14
R COUNTER
LATCH
FUNCTION
LATCH
N COUNTER
LATCH
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
AVDD
SDOUT
MUX
HIGH Z
MUXOUT
13-BIT
N COUNTER
M3 M2 M1
ADF4002
CE AGND DGND
Figure 1.
Rev. D
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ADF4002 Datasheet, Funktion
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to GND1
AVDD to DVDD
VP to GND
VP to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFINA, RFINB to GND
RFINA to RFINB
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
Reflow Soldering
Peak Temperature (60 sec)
Time at Peak Temperature
Transistor Count
CMOS
Bipolar
Rating
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to +5.8 V
−0.3 V to VDD + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to VDD + 0.3 V
±600 mV
−40°C to +85°C
−65°C to +125°C
150°C
260°C
40 sec
6425
303
1 GND = AGND = DGND = 0 V.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ADF4002
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Take proper
precautions for handling and assembly.
THERMAL CHARACTERISTICS
Table 4. Thermal Impedance
Package Type
TSSOP
LFCSP
θJA
150.4
122
Unit
°C/W
°C/W
ESD CAUTION
Rev. D | Page 5 of 20

6 Page









ADF4002 pdf, datenblatt
Data Sheet
ADF4002
REFERENCE COUNTER LATCH MAP
RESERVED
TEST
MODE BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X 0 0 LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)
X = DON’T CARE
R14
R13
R12
..........
R3
R2
R1 DIVIDE RATIO
0
0
0
..........
0
0
11
0
0
0
..........
0
1
02
0
0
0
..........
0
1
13
0
0
0
..........
1
0
04
.
.
.
..........
.
.
..
.
.
.
..........
.
.
..
.
.
.
..........
.
.
..
1
1
1
..........
1
0
0 16380
1
1
1
..........
1
0
1 16381
1
1
1
..........
1
1
0 16382
1
1
1
..........
1
1
1 16383
ABP2
0
0
1
1
ABP1
0
1
0
1
ANTIBACKLASH PULSE WIDTH
2.9ns
NOT ALLOWED
6.0ns
2.9ns
TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION.
LDP
0
1
OPERATION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION.
Figure 16. Reference Counter Latch Map
Rev. D | Page 11 of 20

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