PDF ADP3166 Data sheet ( Hoja de datos )

Número de pieza	ADP3166
Descripción	4-Phase Synchronous Buck Controller
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.com 5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller ADP3166* FEATURES Selectable 2-, 3- or 4-Phase Operation at up to 1 MHz per Phase Differential Sensing Error ±1% over Temperature Logic-Level PWM Outputs for Interface to External High Power Drivers Active Current Balancing between All Output Phases Built-in Power Good Blanking Supports On-the-Fly VID Code Changes 5-Bit Digitally Programmable 0.8 V to 1.55 V Output Short-Circuit Protection with Programmable Latch-Off Delay Overvoltage Protection Crowbar Logic Output APPLICATIONS Desktop PC Power Supplies Next-Generation AMD Processors VRM Modules GENERAL DESCRIPTION The ADP3166 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance AMD processors. It uses an internal 5-bit DAC to read a voltage identification (VID) code directly from the pro- cessor, which is used to set the output voltage between 0.8 V and 1.55 V. The ADP3166 also uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VRM size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switch- ing stages. The ADP3166 includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3166 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output volt- age changes requested by the CPU. ADP3166 is specified over the commercial temperature range of 0°C to 85°C and is available in a 28-lead TSSOP package. FUNCTIONAL BLOCK DIAGRAM VCC 28 ADP3166 EN 11 UVLO SHUTDOWN AND BIAS GND 19 CROWBAR 6 CSREF 2.1V + – DAC + 300mV CSREF + – DAC – 300mV + – PWRGD 10 DELAY ILIMIT 15 EN RAMPADJ RT 14 13 OSCILLATOR CURRENT BALANCING CIRCUIT + –CMP SET EN RESET 27 PWM1 + CMP – + –CMP RESET 2-, 3-, 4-PHASE DRIVER LOGIC RESET 26 PWM2 25 PWM3 + –CMP RESET 24 PWM4 CROWBAR CURRENT LIMIT CURRENT LIMIT CIRCUIT 23 SW1 22 SW2 21 SW3 20 SW4 – 17 CSSUM + 16 CSREF DELAY 12 COMP 9 SOFT START – + + – 18 CSCOMP 8 FB PRECISION REFERENCE VID DAC 7 FBRTN 12345 VID4 VID3 VID2 VID1 VID0 *Patent pending REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. DataSheet4 U .com 1 page www.DataSheet4U.com ADP3166 1 VID4 VCC 28 2 VID3 PWM1 27 + 1␮F 5-BIT CODE 3 VID2 4 VID1 PWM2 26 PWM3 25 5 VID0 PWM4 24 6 CROWBAR SW1 23 7 FBRTN SW2 22 8 FB SW3 21 1k⍀ 9 COMP 10 PWRGD SW4 20 GND 19 1.25V 11 EN 12 DELAY 4.7nF 250k⍀ 13 RT CSCOMP 18 CSSUM 17 CSREF 16 20k⍀ 14 RAMPADJ ILIMIT 15 250k⍀ 12V 100nF 100nF Test Circuit 1. Closed-Loop Output Voltage Accuracy 12V 39k⍀ 1k⍀ + 1V – ADP3166 VCC 28 CSCOMP 18 100nF CSSUM 17 CSREF 16 – + GND 19 VOS = CSCOMP – 1V 40 Test Circuit 2. Positioning Amplifier VOS Test Circuit ADP3166 ADP3166 VCC 12V 28 10k⍀ FB 8 COMP 9 200k⍀ + 80mV – + 1V – 200k⍀ CSCOMP 18 CSSUM 17 CSREF 16 – + GND 19 ⌬VFB = FB – VVID Test Circuit 3. Positioning Voltage Test Circuit REV. 0 DataSheet4 U .com –5– 5 Page www.DataSheet4U.com ADP3166 Soft Start and Current Limit Latch-Off Delay Times Because the soft start and current limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The first step is to set CDLY for the soft start ramp. This ramp is generated with a 20 µA internal current source. The value of RDLY will have a second order impact on the soft- start time because it sinks part of the current source to ground. However, as long as RDLY is kept greater than 200 kΩ, this effect is minor. The value for CDLY can be approximated using CDLY =   20 µA – VVID 2 × RDLY   × tSS VVID (2) where tSS is the desired soft start time. Assuming an RDLY of 390 kΩ and a desired a soft start time of 3 ms, CDLY is 36 nF. The closest standard value for CCS is 39 nF. Once CDLY has been chosen, RDLY can be calculated for the current limit latch off time using RDLY = 1.96 × tDLY CDLY (3) If the result for RDLY is less than 200 kΩ , then a smaller soft start time should be considered by recalculating the equation for CDLY or a longer latch-off time should be used. In no case should RDLY be less than 200 kΩ. In this example, a delay time of 8 ms makes RDLY = 402 kΩ. The closest standard 5% value is 390 kΩ. Inductor Selection The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduc- tion losses in the MOSFETs but allows using smaller-size inductors and, for a specified peak-to-peak transient deviation, less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger-size inductors and more output capacitance for the same peak-to-peak transient deviation. In any multiphase converter, a practical value for the peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the induc- tance, oscillator frequency, and peak-to-peak ripple current in the inductor. Equation 5 can be used to determine the mini- mum inductance based on a given output ripple voltage: ( )IR = VVID × fSW 1– ×L D ( )( )L ≥ VVID × ROD × 1 – n × D fSW ×VRIPPLE (4) (5) Solving Equation 5 for a 10 mV p-p output ripple voltage yields L ≥ 1.5V ×1.9mΩ × (1– 0.375) 330kHz ×10mV = 540 nH If the ripple voltage is less than that designed for, the inductor can be made smaller until the ripple value is met. This will allow opti- mal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. A 600 nH inductor is a good choice for a starting point, and it gives a calculated ripple cur- rent of 6.6 A. The inductor should not saturate at the peak current of 22 A, and should be able to handle the sum of the power dissipation caused by the average current of 18.7 A in the winding and the core loss. Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. A large DCR will cause excessive power losses, while too small a value will lead to increased measurement error. A good rule is to have the DCR be about 1 to 1 1/2 times the static droop resistance (RO). For our example, we are using an inductor with a DCR of 1.6 mΩ. Designing an Inductor Once the inductance and DCR are known, the next step is either to design an inductor or to find a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to keep the accuracy of the system controlled. Using 20% for the inductance and 8% for the DCR (at room temperature) are rea- sonable tolerances that most manufacturers can meet. The first decision in designing the inductor is to choose the core material. There are several possibilities for providing low core loss at high frequencies. Two examples are the powder cores (e.g., Kool-Mµ® from Magnetics, Inc. or Micrometals) and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. The best choices for a core geometry are closed-loop types, such as pot cores, PQ, U, and E cores, or toroids. A good compromise between price and performance are cores with a toroidal shape. There are many useful references for quickly designing a power inductor, such as • Magnetic Designer Software Intusoft (http://www.intusoft.com) • Designing Magnetic Components for High-Frequency DC-DC Converters McLyman, Kg Magnetics ISBN 1-883107-00-8 REV. 0 DataSheet4 U .com –11– 11 Page

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