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PC2100 Schematic ( PDF Datasheet ) - Infineon Technologies

Teilenummer PC2100
Beschreibung 184 - Pin Registered Double Data Rate SDRAM Modules
Hersteller Infineon Technologies
Logo Infineon Technologies Logo 




Gesamt 48 Seiten
PC2100 Datasheet, Funktion
www.DataSheet4U.com
Data Sheet, Rev. 1.1, Apr. 2004
HYS72D32300GBR–[5/6/7]–B
HYS72D643[00/20]GBR–[5/6/7]–B
HYS72D128320GBR–[5/6/7]–B
184 - Pin Registered Double Data Rate SDRAM
Modules
Reg DIMM
DDR SDRAM
Memory Products
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PC2100 Datasheet, Funktion
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HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Overview
1 Overview
1.1 Features
• 184-Pin Registered 8-Byte Dual-In-Line
DDR SDRAM Module for “1U” PC, Workstation and Server main memory applications
• One rank 32M × 72, 64M × 72 and two ranks 64M × 72, 128M × 72 organization
• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V (± 0.2 V) power
supply and a single + 2.6 V (± 0.1 V) power supply for DDR400
• Built with 256-Mbit DDR-I SDRAMs in P-TFBGA-60-1 packages
• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Re-drive for all input signals using register and PLL devices.
• Serial Presence Detect with E2PROM
• Low Profile Modules form factor:
128.95 mm × 28.58 mm × 4.00 mm
133.35 mm × 30.48 mm (1.2”) × 4.00 mm (6.80 mm with stacked components)
• JEDEC standard reference layout for one rank 256MB and 512MB, two ranks 512MB and 1GByte:
PC2700 Registered DIMM Raw Cards A,B,C,D
• Gold plated contacts
Table 1 Performance
Part Number Speed Code
Speed Grade Component
Module
max. Clock @CL3
Frequency @CL2.5
@CL2
fCK3
fCK2.5
fCK2
-5
DDR400B
PC3200-3033
200
166
133
6
DDR333B
PC2700–2533
166
166
133
-7
DDR266A
PC2100-2033
143
133
Unit
MHz
MHz
MHz
1.2 Description
The HYS72D[32/64/128]3[00/20]GBR are low profile versions of the standard Registered DIMM modules with
less/equal 1.2” inch (30.48 mm) height for 1U Server Applications. The Low Profile DIMM versions are available
as 32M × 72 (256MB), 64M × 72 (512MB) and 128M × 72 (1 GB).
The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors
are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using
the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
available to the customer.
Data Sheet
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6 Rev. 1.1, 2004-04
10102003-01E2-HPA8

6 Page









PC2100 pdf, datenblatt
www.DataSheet4U.com
Front View Standard Height
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
PIN 1
Back View
PIN 93
PIN 52
PIN 53
PIN 144
PIN 145
PIN 92
PIN 184
Front View 1U Height
PIN 1
Back View
PIN 93
PIN 52
PIN 144
PIN 53
PIN 145
PIN 92
PIN 184
Figure 1 PCB with Pin Connector
Data Sheet
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12
Rev. 1.1, 2004-04
10102003-01E2-HPA8

12 Page





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