Datenblatt-pdf.com


ADS5541 Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS5541
Beschreibung (ADS554x) 80MSPS Analog-to-Digital Converter
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 30 Seiten
ADS5541 Datasheet, Funktion
www.DataSheet4U.com
ADS5542
SBAS308A − MAY 2004 − REVISED MARCH 2005
14ĆBit, 80MSPS
AnalogĆtoĆDigital Converter
FEATURES
D 14-Bit Resolution
D 80MSPS Sample Rate
D High SNR: 72.9dBFS at 100 MHz fIN
D High SFDR: 88dBc at 100 MHz fIN
D 2.3VPP Differential Input Voltage
D Internal Voltage Reference
D 3.3V Single-Supply Voltage
D Analog Power Dissipation: 545mW
− Output Buffer Power: 129mW
D TQFP-64 PowerPADE Package
D Recommended Op Amps:
THS3202, THS3201, THS4503,
OPA695, OPA847
DESCRIPTION
D Pin-Compatible with:
− ADS5500 (14-Bit, 125MSPS)
− ADS5541 (14-Bit, 105MSPS)
− ADS5520 (12-Bit, 125MSPS)
− ADS5521 (12-Bit, 105MSPS)
− ADS5522 (12-Bit, 80MSPS)
APPLICATIONS
D Wireless Communication
− Communication Receivers
− Base Station Infrastructure
D Test and Measurement Instrumentation
D Single and Multichannel Digital Receivers
D Communication Instrumentation
− Radar, Infrared
D Video and Imaging
D Medical Equipment
D Military Equipment
The ADS5542 is a high-performance, 14-bit, 80MSPS analog-to-digital converter (ADC). To provide a complete converter
solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for
applications demanding the highest speed and highest dynamic performance in very little space, the ADS5542 has
excellent analog power dissipation of 545mW and output buffer power dissipation of 129mW from a 3.3V single-supply
voltage. This allows an even higher system integration density. The provided internal reference simplifies system design
requirements. Parallel CMOS compatible output ensures seamless interfacing with common logic.
The ADS5542 is available in a 64-pin TQFP PowerPAD package and is pin-compatible with the ADS5500, ADS5541,
ADS5520, ADS5521, and ADS5522. This device is specified over the full temperature range of −40°C to +85°C.
AVDD
DRVDD
CLK+
CLK
Timing Circuitry
CLKOUT
VIN+
VIN
S&H
CM Internal
Reference
14−Bit
Pipeline
ADC Core
Digital
Error
Correction
Control Logic
Serial Programming Register
Output
Control
D...0
D13
ADS5542
OVR
DFS
AGND
SEN SDATA SCLK
DRGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2004−2005, Texas Instruments Incorporated
DataSheet4 U .com
www.ti.com






ADS5541 Datasheet, Funktion
www.DataSheet4U.com
ADS5542
SBAS308A − MAY 2004 − REVISED MARCH 2005
TIMING CHARACTERISTICS
www.ti.com
Analog
Input
Signal
Sample
N
tA
N+1
Input Clock
Output Clock
N+2
N+3
tSTART
N+4
Data Out
(D0−D13)
N − 17
N − 16
N − 15
tEND
N − 14 N − 13
16.5 Clock Cycles
N + 14
N−3
N + 15
N + 16
N−2
N−1
Data Invalid
N + 17
tPDI = tSTART + t SETUP
tSETUP
N
tHOLD
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing
matches closely with the specified values.
Figure 1. Timing Diagram
TIMING CHARACTERISTICS(1)(2)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 80MSPS, 50% clock duty cycle, AVDD =
DRVDD = 3.3V, and 3VPP differential clock, unless otherwise noted.(2)
PARAMETER
DESCRIPTION
MIN TYP MAX UNIT
Switching Specification
Aperture delay, tA
Aperture jitter (uncertainty)
Input CLK falling edge to data sampling point
Uncertainty in sampling instant
1 ns
300 fs
Data setup time, tSETUP
Data hold time, tHOLD
Input clock to output data valid
start, tSTART(4)
Data valid(3) to 50% of CLKOUT rising edge
50% of CLKOUT rising edge to data becoming invalid(3)
Input clock to Data valid start delay
3.2 4.2
1.8 3
3.8
5
ns
ns
ns
Input clock to output data valid end,
tEND(4)
Input clock to Data valid end delay
8.4 11
ns
Data rise time, tRISE
Data rise time measured from 20% to 80% of DRVDD
5.6 6.1
ns
Data fall time, tFALL
Data fall time measured from 80% to 20% of DRVDD
4.4 5.1
ns
Output enable (OE) to data output Time required for outputs to have stable timings with regard to Input
delay
Clock(5) after OE is activated
Clock
1000 Cycles
(1) Timing parameters are ensured by design and characterization, and not tested in production.
(2) See Table 5 in the Application Information section for timing information at additional sampling frequencies.
(3) Data valid refers to 2.0V for LOGIC HIGH and 0.8V for LOGIC LOW.
(4) Refer to the Output Information section for details on using the input clock for data capture.
(5) Data outputs are available within a clock from assertion of OE; however it takes 1000 clock cycles to ensure stable timing with respect to input
clock.
6
DataSheet4 U .com

6 Page









ADS5541 pdf, datenblatt
www.DataSheet4U.com
ADS5542
SBAS308A − MAY 2004 − REVISED MARCH 2005
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to
the power of the first eight harmonics (PD).
THD
+
10Log10
PS
PD
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the highest
other spectral component (either spur or harmonic).
SFDR is typically given in units of dBc (dB to carrier).
www.ti.com
Two-Tone Intermodulation Distortion
IMD3 is the ratio of the power of the fundamental (at
frequencies f1 and f2) to the power of the worst spectral
component at either frequency 2f1−f2 or 2f2−f1. IMD3 is
either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the
reference, or dBFS (dB to Full-Scale) when the power
of the fundamental is extrapolated to the converter’s
full-scale range.
12
DataSheet4 U .com

12 Page





SeitenGesamt 30 Seiten
PDF Download[ ADS5541 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ADS5541(ADS554x) 80MSPS Analog-to-Digital ConverterBurr-Brown Corporation
Burr-Brown Corporation
ADS554114-Bit 105MSPS Analog-to-Digital Converter (Rev. C)Texas Instruments
Texas Instruments
ADS5542(ADS554x) 80MSPS Analog-to-Digital ConverterBurr-Brown Corporation
Burr-Brown Corporation
ADS554214-Bit 80 MSPS Analog-to-Digital Converter (Rev. D)Texas Instruments
Texas Instruments
ADS554514 Bit 170 MSPS ADC With DDR LVDS/CMOS Outputs (Rev. C)Texas Instruments
Texas Instruments

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche