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PDF ADM1185 Data sheet ( Hoja de datos )
| Número de pieza | ADM1185 | |
| Descripción | Quad Voltage Monitor and Sequencer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Quad Voltage Monitor and Sequencer
ADM1185
FEATURES
Powered from 2.7 V to 5.5 V on the VCC pin
Monitors 4 supplies via 0.8% accurate comparators
Logical core with internal timeouts provides power supply
sequencing and fault protection
4 inputs can be programmed to monitor different voltage
levels with resistor dividers
3 open-drain enable outputs
Open-drain power-good output (PWRGD)
10-lead MSOP
APPLICATIONS
Monitor and alarm functions
Power supply sequencing
Telecommunication and data communication equipment
PCs/servers
FUNCTIONAL BLOCK DIAGRAM
VCC
VIN1
VIN2
VIN3
VIN4
ADM1185
REF = 0.6V
REF = 0.6V
REF = 0.6V
REF = 0.6V
POWER AND
REFERENCE
REF = 0.6V
GENERATOR
STATE
MACHINE
CORE
OUT1
OUT2
OUT3
PWRGD
GND
GENERAL DESCRIPTION
The ADM1185 is an integrated, 4-channel, voltage monitoring
and sequencing device. A 2.7 V to 5.5 V power supply is
required on the VCC pin to power the device.
Four precision comparators monitor four voltage rails.
All comparators have a 0.6 V reference with a worst-case
accuracy of 0.8%. Resistor networks that are external to the
VIN1, VIN2, VIN3, and VIN4 pins set the trip points for
the monitored supply rails.
A digital core interprets the status of the comparator outputs.
Figure 1.
Internal time delays can be used for sequencing the startup of
subsequent power supplies enabled by the outputs. Supplies
falling out of range are also detected and, as a result, appropriate
outputs are disabled.
The ADM1185 has four open-drain outputs. In a typical
configuration, OUT1 to OUT3 are used to enable power
supplies, while PWRGD is a common power-good output,
indicating the status of all monitored supplies.
The ADM1185 is available in a 10-lead mini small outline
package (MSOP).
3.3V IN
APPLICATIONS DIAGRAM
2.5V OUT
1.8V OUT
1.2V OUT
VCC
ADM1185
VIN1
OUT1
VIN2
OUT2
VIN3
OUT3
VIN4
GND PWRGD
POWER
GOOD
IN
REGULATOR1
EN OUT
GND
IN
REGULATOR2
EN OUT
GND
2.5V OUT
1.8V OUT
IN
REGULATOR3
EN OUT
GND
1.2V OUT
Figure 2.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
1 page  
ADM1185
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter
VCC Pin
VINx Pins
OUTx, PWRGD Pins
Storage Temperature Range
Operating Temperature Range
Lead Temperature Soldering (10 sec)
Junction Temperature
Rating
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
10-Lead MSOP
θJA
137.5
Unit
°C/W
ESD CAUTION
Rev. B | Page 4 of 16
5 Page 
ADM1185
VOLTAGE MONITORING AFTER POWER-ON
Once PWRGD is asserted, the logical core latches into a different
mode of operation. During the initial power-up phase, each
output directly depends on an input (for example, VIN3 asserting
causes OUT3 to assert). When power-up is complete, this
function is redundant.
Once in the PWRGD state, the following behavior can be observed:
• If the main 3.3 V supply monitored via VIN1 faults in the
power-good state, the PWRGD output is deasserted to
warn the downstream controller. All outputs (OUT1 to
OUT3) are immediately turned off, disabling all locally
generated supplies.
• If a supply monitored by VIN2 to VIN4 fails, the PWRGD
output is deasserted to warn the controller, but the other
outputs are not deasserted.
Figure 20 and Figure 21 show waveforms that highlight the
behavior of the ADM1185 under various fault situations during
normal operation (that is, in the mode of operation after
PWRGD is asserted).
STATE1 START
VIN1 = OK
(DELAY = 190ms TYP)
STATE2 OUT1
ON
VIN1 = FAULT
VIN2 = OK
STATE3 OUT1, OUT2
ON
VIN1 = FAULT
VIN3 = OK
STATE4 OUT1, OUT2, OUT3
ON
VIN1 = FAULT
VIN4 = OK
(DELAY = 100ms MIN)
STATE5 PWRGD
VIN1 = FAULT
VIN2. VIN3. VIN4 = FAULT
Figure 19. Flow Diagram Highlighting the Different Modes of Operation
of the Logical Core
Rev. B | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADM1185.PDF ] | |
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