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PDF AD7693 Data sheet ( Hoja de datos )
| Número de pieza | AD7693 | |
| Descripción | 500 kSPS PulSAR Differential ADC in MSOP/QFN | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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16-Bit, +/-0.65 LSB INL, 500 kSPS PulSAR®
Differential ADC in MSOP/QFN
Preliminary Technical Data
AD7693
FEATURES
16-bit resolution with no missing codes
Throughput: 500 kSPS
INL: +/-0.25 LSB typical, ±0.65 LSB max (±10 ppm of FSR)
Dynamic range: 96.5 dB typical @ 500 kSPS
SINAD: 96 dB typical @ 1 kHz, REF = 5V
THD: −120 dB typical @ 1 kHz. REF = 5V
True differential analog input range: ±VREF
0 V to VREF with VREF up to VDD on both inputs
No pipeline delay
Single-supply 5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible
Daisy-chain multiple ADCs and busy indicator
Power dissipation
4 mW @ 5 V/100 kSPS
40 μW @ 5 V/1 kSPS
Standby current: 1 nA
10-lead package: MSOP (MSOP-8 size) and
3 mm × 3 mm QFN1 (LFCSP) (SOT-23 size)
Pin-for-pin compatible with the AD7687, AD7688 and 18-bit
AD7690 and AD7691
APPLICATIONS
Battery-powered equipment
Data acquisitions
Seismic data acquisition systems
DVMs
Instrumentation
Medical instruments
Figure 1. Integral Nonlinearity vs. Code
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
APPLICATION DIAGRAM
+2.5V TO +5V +5V
±10V, ±5V, ...
ADA4941-1
REF VDD VIO
IN+ SDI
SCK
IN–
GND
SDO
CNV
+1.8V TO VDD
3- OR 4-WIRE
INTERFACE
(SPI, DAISY CHAIN, CS)
AD7693
Figure 2.
Table 1. MSOP, QFN1 (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC
Type
100
kSPS
250
kSPS
400 kSPS
to
500 kSPS
18-Bit
AD7691 AD7690
16-Bit True
Differential
16-Bit Pseudo
Differential/
Unipolar
14-Bit
AD7684
AD7683
AD7680
AD7940
AD7687
AD7685
AD7694
AD7942
AD7688
AD7693
AD7686
AD7946
ADC
Driver
ADA4941-1
ADA4841-x
ADA4941-1
ADA4841-x
ADA4841-x
ADA4841-x
1 QFN package in development. Contact sales for samples and availability.
GENERAL DESCRIPTION
The AD7693 is a 16-bit, successive approximation, analog-to-
digital converter (ADC) that operates from a single power supply,
VDD. It contains a low power, high speed, 16-bit sampling ADC
with no missing codes, an internal conversion clock, and a
versatile serial interface port. On the CNV rising edge, it
samples the voltage difference between the IN+ and IN− pins.
The voltages on these pins swing in opposite phase between 0 V
and REF. The reference voltage, REF, is applied externally and
can be set up to the supply voltage, VDD.
Its power scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.
The AD7693 is housed in a 10-lead MSOP or a 10-lead QFN1
(LFCSP) with operation specified from −40°C to +85°C.
1 QFN package in development. Contact sales for samples and availability.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
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Preliminary Technical Data
AD7693
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 4. 1
Parameter
Symbol Min Typ
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 4.5 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with BUSY Indicator)
VIO Above 4.5 V
VIO Above 2.3 V
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
0.5
400
2.0
10
15
17
18
19
20
7
7
4
15
0
5
10
3
4
1 See Figure 3 and Figure 4 for load conditions.
Max
1.6
14
15
16
17
15
18
22
25
15
26
Unit
μs
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Rev. PrB | Page 5 of 24
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Preliminary Technical Data
1000
fS = 100kSPS
750
VDD
500
250
0
4.50
1000
VIO
4.75 5.00 5.25
SUPPLY (V)
Figure 19. Operating Currents vs. Supply
5.50
750
500
250
VDD + VIO
0
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
Figure 20. Power-Down Currents vs. Temperature
1000
fS = 100kSPS
VDD
750
500
250
–6
–55 –35 –15
VIO
5 25 45 65
SUPPLY (V)
85 105 125
Figure 21. Operating Currents vs. Temperature
AD7693
Figure 22. Offset and Gain Error vs. Temperature
25
20
15
VDD = 5V, 85°C
10
VDD = 5V, 25°C
5
0
0 20 40 60 80 100 120
SDO CAPACITIVE LOAD (pF)
Figure 23. tDSDO Delay vs. Capacitance Load and Supply
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Rev. PrB | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD7693.PDF ] | |
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