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ADL5306 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADL5306
Beschreibung 60 dB Range (100 nA to 100 UA) Low Cost Logarithmic Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
ADL5306 Datasheet, Funktion
www.DataSheet4U.com
FEATURES
Optimized for fiber optic photodiode interfacing
Measures current over 3 decades
Law conformance 0.1 dB from 100 nA to 100 μA
Single- or dual-supply operation (3 V to ±5.5 V total)
Full log-ratio capabilities
Temperature stable
Nominal slope of 10 mV/dB (200 mV/decade)
Nominal intercept of 1 nA (set by external resistor)
Optional adjustment of slope and intercept
Rapid response time for a given current level
Miniature 16-lead chip scale package (LFCSP 3 mm × 3 mm)
Low power: ~5 mA quiescent current
APPLICATIONS
Low cost optical power measurement
Wide range baseband logarithmic compression
Measurement of current and voltage ratios
Optical absorbance measurement
GENERAL DESCRIPTION
The ADL5306is a low cost microminiature logarithmic converter
optimized for determining optical power in fiber optic systems. The
ADL5306 is derived from the AD8304 and AD8305 translinear
logarithmic converters. This family of devices provides wide
measurement dynamic range in a versatile and easy-to-use form. A
single-supply voltage between 3 V and 5.5 V is adequate; dual
supplies may optionally be used. Low quiescent current (5 mA
typical) permits use in battery-operated applications.
IPD, the 100 nA to 100 µA input current applied to the INPT pin, is
the collector current of an optimally scaled NPN transistor that
converts this current to a voltage (VBE) with a precise logarithmic
relationship. A second converter is used to handle the reference
current, IREF, applied to IREF. These input nodes are biased slightly
above ground (0.5 V). This is generally acceptable for photodiode
applications where the anode does not need to be grounded.
Similarly, this bias voltage is easily accounted for in generating IREF.
The logarithmic front end’s output is available at VLOG.
The basic logarithmic slope at this output is 200 mV/decade
(10 mV/dB) nominal; a 60 dB range corresponds to a 600 mV
output change. When this voltage (or the buffer output) is applied
to an ADC that permits an external reference voltage to be
employed, the ADL5306’s 2.5 V voltage reference output at VREF
can be used to improve scaling accuracy.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
DataSheet4 U .com
60 dB Range (100 nA to 100 µA)
Low Cost Logarithmic Converter
ADL5306
FUNCTIONAL BLOCK DIAGRAM
NC
VREF
VPOS +5V
( )0.2 log10
IPD
1nA
VOUT
RREF
200k
0.5V
20k
2.5V
BIAS
80k
GENERATOR
COMM
VBIAS
IREF
1k
1nF
IPD INPT
VBE2
14.2k
SCAL
BFIN
Q2 TEMPERATURE ILOG
Q1
COMPENSATION
451VLOG
VBE1
6.69k
1kVSUM
1nF
1nF
0.5V
VNEG
COMM
COMM
03727-0-001
Figure 1. Functional Block Diagram
The logarithmic intercept (reference current) is nominally
positioned at 1 nA by using the externally generated, 100 µA IREF
current provided by a 200 kΩ resistor connected between VREF, at
2.5 V, and IREF, at 0.5 V. The intercept can be adjusted over a
narrow range by varying this resistor. The part can also operate in a
log-ratio mode, with limited accuracy, where the numerator and
denominator currents are applied to INPT and IREF, respectively.
A buffer amplifier is provided to drive substantial loads, raise the
basic 10 mV/dB slope, serve as a precision comparator (threshold
detector), or implement low-pass filters. Its rail-to-rail output stage
can swing to within 100 mV of the positive and negative supply
rails, and its peak current-sourcing capacity is 25 mA.
A fundamental aspect of translinear logarithmic converters is that
small-signal bandwidth falls as current level diminishes, and low
frequency noise-spectral density increases. At the 100 nA level, the
ADL5306’s bandwidth is about 100 kHz; it increases in proportion
to IPD up to a maximum of about 10 MHz. The increase in noise
level at low currents can be addressed by using a buffer amplifier to
realize low-pass filters of up to three poles.
The ADL5306 is available in a 16-lead LFCSP package and is
specified for operation from–40°C to +85°C.
Protected by US Patents 4,604,532 and 5,519,308; other patents pending.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.






ADL5306 Datasheet, Funktion
www.DataSheet4U.com
ADL5306
TYPICAL PERFORMANCE CHARACTERISTICS
(VP = 5 V, VN = 0 V, RREF = 200 kΩ, TA = 25°C, unless otherwise noted.)
1.2
TA = –40°C, 0°C, +25°C, +70°C, +85°C
VN = 0V
1.0
0.8
0.6
0.4
0.2
0
10n
100n
1µ 10µ
IPD (A)
100µ
1m
03727-0-003
Figure 3. VLOG vs. IPD for Multiple Temperatures
1.4
TA = –40°C, 0°C, +25°C, +70°C, +85°C
1.2 VN = 0V
1.0
0.8
0.6
0.4
0.2
0
10n 100n
1µ 10µ
IREF (A)
100µ
1m
03727-0-004
Figure 4. VLOG vs. IREF for Multiple Temperatures
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10n
100nA
1µA
10µA
100µA
100n
1µ 10µ
IPD (A)
100µ
Figure 5. VLOG vs. IPD for Multiple Values of IREF
(Decade Steps from 10 nA to 1 mA)
1m
03727-0-005
1.5
TA = –40°C, 0°C, +25°C, +70°C, +85°C
VN = 0V
1.0
0.5
+85°C
+70°C
0
–0.5
–1.0
0°C
–40°C
+25°C
–1.5
10n
100n
1µ 10µ
IPD (A)
100µ
1m
03727-0-006
Figure 6. Law Conformance Error vs. IPD (IREF = 10 µA) for Multiple
Temperatures, Normalized to 25°C
1.5
TA = –40°C, 0°C, +25°C, +70°C, +85°C
VN = 0V
1.0
0.5
+85°C
+70°C
0
–0.5
–1.0
+25°C
–40°C 0°C
–1.5
10n
100n
1µ 10µ
IREF (A)
100µ
1m
03727-0-007
Figure 7. Law Conformance Error vs. IREF (IPD = 10 µA) for Multiple
Temperatures, Normalized to 25°C
0.3
0.2
0.1
10µA
100µA
0
1µA
–0.1
100nA
–0.2
–0.3
10n
100n
1µ 10µ
IPD (A)
100µ
1m
03727-0-008
Figure 8. Law Conformance Error vs. IPD for Multiple Values of IREF
(Decade Steps from 10 nA to 1 mA)
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ADL5306 pdf, datenblatt
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ADL5306
The use of a negative supply, VN, allows the summing node to be
placed at ground level whenever the input transistor (Q1 in
Figure 1) has a sufficiently negative bias on its emitter. When
VN = –0.5 V, the VCE of Q1 and Q2 will be the same value as in
the default case when VSUM is grounded. This bias need not be
accurate, and a poorly defined source can be used. However, the
source must be able to support the quiescent current as well as
the INPT and IREF signal current. For example, it may be
convenient to utilize a forward-biased junction voltage of about
0.7 V or a Schottky barrier voltage of a little over 0.5 V. With the
summing node at ground, the ADL5306 may now be used as a
voltage-input log amp, at either the numerator input INPT or
the denominator input IREF by inserting a suitably scaled
resistor from the voltage source to the relevant pin. The overall
accuracy for small input voltages is limited by the voltage offset
at the inputs of the JFET op amps.
The use of a negative supply also allows the output to swing
below ground, thereby allowing the intercept to correspond to a
midrange value of IPD. However, the voltage VLOG remains
referenced to the ACOM pin, and while VLOG does not swing
negative for default operating conditions, it is free to do so.
Thus, adding a resistor from VLOG to the negative supply
lowers all values of VLOG, which raises the intercept. The
disadvantage of this method is that the slope is reduced by the
shunting of the external resistor, and the poorly defined ratio of
on-chip and off-chip resistance causes errors in both the slope
and intercept. A more accurate method for repositioning the
intercept follows.
CHARACTERIZATION METHODS
During the characterization of the ADL5306, the device was
treated as a precision current-input logarithmic converter,
because it is impractical to generate accurate photocurrents by
illuminating a photodiode. The test currents were generated by
using either a well-calibrated current source, such as the
Keithley 236, or a high value resistor from a voltage source to
the input pin. Great care is needed when using very small input
currents. For example, the triax output connection from the
current generator was used with the guard tied to VSUM. The
input trace on the PC board was guarded by connecting
adjacent traces to VSUM.
These measures are needed to minimize the risk of leakage
current paths. With 0.5 V as the nominal bias on the INPT pin,
a leakage-path resistance of 1 GΩ to ground would subtract
0.5 nA from the input, which amounts to a –0.44 dB error for a
10 nA source current. Additionally, the very high output
resistance at the input pins and the long cables commonly
needed during characterization allow 60 Hz and RF emissions
to introduce substantial measurement errors. Careful guarding
techniques are essential to reducing the pickup of these
spurious signals.
KEITHLEY 236
KEITHLEY 236
TRIAX CONNECTORS
(SIGNAL – INPT AND IREF
GUARD – VSUM
SHIELD – GROUND)
VREF VNEG VPOS
IREF ADL5306
VOUT
CHARACTERIZATION BFIN
INPT
BOARD
VLOG
VSUM
RIBBON
CABLE
DC MATRIX / DC SUPPLIES / DMM
03727-0-024
Figure 24. Primary Characterization Setup
The primary characterization setup shown in Figure 24 is used
to measure VREF, the static (dc) performance, logarithmic
conformance, slope and intercept, the voltages appearing at Pins
VSUM, INPT, and IREF, and the buffer offset and VREF drift
with temperature. In some cases, a fixed resistor between Pins
VREF and IREF was used in place of a precision current source.
For the dynamic tests, including noise and bandwidth
measurements, more specialized setups are required. This
includes close attention to the input stabilizing networks; for
example, to ensure stable operation over the full current range
of IREF and temperature extremes, filter components C1 = 4.7 nF
and R13 = 2 kare used at Pin IREF to ground.
HP3577A
NETWORK ANALYZER
OUTPUT INPUT R INPUT A INPUT B
+IN B
AD8138
EVALUATION
BOARD
A
BNC-T
AD8138 PROVIDES DC OFFSET
16 15 14 13
COMM COMM COMM COMM
1 NC
VOUT 12
2 VREF
SCAL 11
ADL5306
3 IREF
BFIN 10
4 INPT
VLOG 9
VSUM VNEG VNEG VPOS
5678
+VS
0.1µF
03727-0-025
Figure 25. Configuration for Buffer Amplifier Bandwidth Measurement
Figure 25 shows the configuration used to measure the buffer
amplifier bandwidth. The AD8138 evaluation board includes
provisions to offset VLOG at the buffer input, allowing
measurements over the full range of IPD using a single supply.
The network analyzer input impedances are set to 1 MΩ.
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