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PDF P83C661X2 Data sheet ( Hoja de datos )
| Número de pieza | P83C661X2 | |
| Descripción | (P83C661X2) 80C51 8-bit microcontroller family | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
P83C660X2, P87C660X2
P83C661X2, P87C661X2
80C51 8-bit microcontroller family
16KB OTP/ROM, 512B RAM low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz), two 400KB I2C
interfaces
Product data
Supersedes data of 2003 Jun 19
2003 Oct 02
Philips
Semiconductors
DataSheet4 U .com
1 page  
www.DataSheet4U.com
Philips Semiconductors
80C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2C interfaces
Product data
P8xC660X2/661X2
BLOCK DIAGRAM (CPU-ORIENTED)
VCC
VSS
RAM ADDR
REGISTER
RAM
P0.0–P0.7
PORT 0
DRIVERS
PORT 0
LATCH
P2.0–P2.7
PORT 2
DRIVERS
PORT 2
LATCH
OTP
MEMORY
B
REGISTER
ACC
TMP2
TMP1
STACK
POINTER
8
PROGRAM
ADDRESS
REGISTER
PSEN
ALE
EAVPP
RST
TIMING
AND
CONTROL
PD
OSCILLATOR
XTAL1
XTAL2
ALU
PSW
SFRs
TIMERS
P.C.A.
BUFFER
PC
INCRE-
MENTER
8
PROGRAM
COUNTER
16
PORT 1
LATCH
SERIAL
I2C PORT
SERIAL
I2C PORT
PORT 1
DRIVERS
P1.0–P1.7
SDA
SCL
SDA1
SCL1
DPTR’S
MULTIPLE
PORT 3
LATCH
SERIAL
UART
PORT
PORT 3
DRIVERS
P3.0–P3.7
TxD RxD
SU01761
2003 Oct 02
DataSheet4 U .com
5
5 Page 
www.DataSheet4U.com
Philips Semiconductors
80C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2C interfaces
Product data
P8xC660X2/661X2
CLOCK CONTROL REGISTER (CKCON)
This device allows control of the 6-clock/12-clock mode by means of
both an SFR bit (X2) and an OTP bit. The OTP clock control bit
OX2, when programmed by a parallel programmer (6-clock mode),
supersedes the X2 bit (CKCON.0). The CKCON register is shown
below in Figure 1.
CKCON Address = 8Fh
Not Bit Addressable
Reset Value = x0000000B
76543210
– – – – – – – X2
BIT
CKCON.7
CKCON.6
CKCON.5
CKCON.4
CKCON.3
CKCON.2
CKCON.1
CKCON.0
SYMBOL
–
X2
FUNCTION
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
CPU clock; 1 = 6 clocks for each machine cycle, 0 = 12 clocks for each machine cycle
SU01689
Figure 1. Clock control (CKCON) register
Also please note that the clock divider applies to the serial port for
modes 0 & 2 (fixed baud rate modes). This is because modes 1 & 3
(variable baud rate modes) use either Timer 1 or Timer 2.
Below is the truth table for the CPU clock mode.
Table 1.
OX2 clock mode bit
(can only be set by
parallel programmer)
X2 bit
(CKCON.0)
CPU clock mode
erased
0 12-clock mode
(default)
erased
1 6-clock mode
programmed
X
6-clock mode
RESET
A reset is accomplished by holding the RST pin HIGH for at least
two machine cycles (12 oscillator periods in 6-clock mode, or
24 oscillator periods in 12-clock mode), while the oscillator is running.
To ensure a good power-on reset, the RST pin must be HIGH long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
VCC and RST must come up at the same time for a proper start-up.
Ports 1, 2, and 3 will asynchronously be driven to their reset
condition when a voltage above VIH1 (min.) is applied to RST.
The value on the EA pin is latched when RST is deasserted and has
no further effect.
2003 Oct 02
DataSheet4 U .com
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| PDF Descargar | [ Datasheet P83C661X2.PDF ] | |
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