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ADM1064 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADM1064
Beschreibung Super Sequencer with Voltage Readback ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADM1064 Datasheet, Funktion
Data Sheet
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP4 (VPx)
5 dual-function inputs, VX1 to VX5 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable driver outputs, PDO1 to PDO10 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
SE implements state machine control of PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
12-bit ADC for readback of all supervised voltages
2 auxiliary (single-ended) ADC inputs
Reference input (REFIN) has 2 input options
Driven directly from 2.048 V (±0.25%) REFOUT pin
More accurate external reference for improved ADC
performance
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 40-lead LFCSP and 48-lead TQFP packages
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
Rev. E
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Super Sequencer with
Voltage Readback ADC
ADM1064
FUNCTIONAL BLOCK DIAGRAM
AUX1 AUX2
REFIN REFOUT REFGND SDA SCL A1 A0
ADM1064
VREF
SMBus
INTERFACE
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
AGND
12-BIT
SAR ADC
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
SEQUENCING
ENGINE
EEPROM
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
VDD
ARBITRATOR
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND
VDDCA P
VCCP
GND
Figure 1.
GENERAL DESCRIPTION
The ADM1064 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems. In addition
to these functions, the ADM1064 integrates a 12-bit ADC that
can be used to accurately read back up to 12 separate voltages.
The device also provides up to 10 programmable inputs for moni-
toring undervoltage faults, overvoltage faults, or out-of-window
faults on up to 10 supplies. In addition, 10 programmable outputs
can be used as logic enables. Six of these programmable outputs can
provide up to a 12 V output for driving the gate of an N-FET
that can be placed in the path of a supply.
For more information about the ADM1064 register map, refer
to the AN-698 Application Note.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADM1064 Datasheet, Funktion
Data Sheet
ADM1064
SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPx = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VH, VPx
VPx
VH
VDDCAP
CVDDCAP
POWER SUPPLY
Supply Current, IVH, IVPx
Additional Currents
All PDO FET Drivers On
Current Available from VDDCAP
ADC Supply Current
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH Pin
Input Impedance
Input Attenuator Error
Detection Ranges
High Range
Midrange
VPx Pins
Input Impedance
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VXx Pins
Input Impedance
Detection Ranges
Ultralow Range
Absolute Accuracy
Threshold Resolution
Digital Glitch Filter
ANALOG-TO-DIGITAL CONVERTER
Signal Range
Min Typ Max Unit
3.0 V
6.0 V
14.4 V
2.7 4.75 5.4 V
10 μF
4.2 6
mA
1
2
1
10
mA
mA
mA
mA
6
2.5
2.5
1.25
0.573
1
0.573
0
52
±0.05
%
14.4 V
6V
52
±0.05
%
6
3
1.375
V
V
V
1.375 V
±1 %
8 Bits
0 μs
100 μs
VREFIN V
Input Reference Voltage on REFIN Pin, VREFIN
Resolution
INL
Gain Error
2.048
12
±2.5
±0.05
V
Bits
LSB
%
Test Conditions/Comments
Minimum supply required on one of VH, VPx pins
Maximum VDDCAP = 5.1 V, typical
VDDCAP = 4.75 V
Regulated LDO output
Minimum recommended decoupling capacitance
VDDCAP = 4.75 V, PDO1 to PDO10 off, ADC off
VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA
each, PDO7 to PDO10 off
Maximum additional load that can be drawn from all
PDO pull-ups to VDDCAP
Running round-robin loop
1 ms duration only, VDDCAP = 3 V
Midrange and high range
Low range and midrange
No input attenuation error
No input attenuation error
VREF error + DAC nonlinearity + comparator offset error
+ input attenuation error
Minimum programmable filter length
Maximum programmable filter length
The ADC can convert signals presented to the VH,
VPx, and VXx pins; VPx and VH input signals are
attenuated depending on the selected range; a signal
at the pin corresponding to the selected range is
from 0.573 V to 1.375 V at the ADC input.
Endpoint corrected, VREFIN = 2.048 V
VREFIN = 2.048 V
Rev. E | Page 5 of 31

6 Page









ADM1064 pdf, datenblatt
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
6
5
4
3
2
1
0
0123456
VVP1 (V)
Figure 5. VVDDCAP vs. VVP1
6
5
4
3
2
1
0
0 2 4 6 8 10 12 14 16
VVH (V)
Figure 6. VVDDCAP vs. VVH
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
1234
VVP1 (V)
Figure 7. IVP1 vs. VVP1 (VP1 as Supply)
5
6
ADM1064
180
160
140
120
100
80
60
40
20
0
0
12345
VVP1 (V)
Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)
6
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
2 4 6 8 10 12 14 16
VVH (V)
Figure 9. IVH vs. VVH (VH as Supply)
350
300
250
200
150
100
50
0
0
12345
VVH (V)
Figure 10. IVH vs. VVH (VH Not as Supply)
6
Rev. E | Page 11 of 31

12 Page





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