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ADN2816 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADN2816
Beschreibung Continuous Rate 12.3 Mb/s to 675 Mb/s Clock and Data Recovery IC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 27 Seiten
ADN2816 Datasheet, Funktion
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Preliminary Technical Data
Continuous Rate 12.3 Mb/s to 675 Mb/s Clock and
Data Recovery IC
ADN2816
FEATURES
Serial data input: 12.3 Mb/s to 675 Mb/s
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Patented clock recovery architecture
No reference clock required
Loss of lock indicator
I2C™ interface to access optional features
Single-supply operation: 3.3 V
Low power: 300 mW typical
5 mm × 5 mm 32-lead LFCSP, Pb Free
APPLICATIONS
SONET OC-1/3/12 and all associated FEC rates
Fibre Channel, ESCON, Fast Ethernet, SDI, etc.
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers
PRODUCT DESCRIPTION
The ADN2816 provides the receiver functions of quantization
and clock and data recovery for continuous data rates from 12.3
Mb/s to 675 Mb/s. The ADN2816 automatically locks to all data
rates without the need for an external reference clock or
programming. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance.
All specifications are quoted for −40°C to +85°C ambient
temperature, unless otherwise noted.
The ADN2816 is available in a compact 5 mm × 5 mm 32-lead
chip scale package.
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FUNCTIONAL BLOCK DIAGRAM
REFCLKP/N
(OPTIONAL)
LOL
CF1
CF2 VCC VEE
PIN
NIN
VREF
FREQUENCY
DETECT
LOOP
FILTER
BUFFER
PHASE
SHIFTER
PHASE
DETECT
LOOP
FILTER
VCO
DATA
RE-TIMING
2
2
DATAOUTP/N CLKOUTP/N DRVCC DRVEE DVCC DVEE
Figure 1.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






ADN2816 Datasheet, Funktion
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ADN2816
ABSOLUTE MAXIMUM RATINGS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47
µF, SLICEP = SLICEN = VEE, unless otherwise noted.
Table 4.
Parameter
Supply Voltage (VCC)
Minimum Input Voltage (All Inputs)
Maximum Input Voltage (All Inputs)
Maximum Junction Temperature
Storage Temperature
Lead Temperature (Soldering 10 s)
Rating
4.2 V
VEE − 0.4 V
VCC + 0.4 V
125°C
−65°C to +150°C
300°C
Preliminary Technical Data
Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
32-LFCSP, 4-layer board with exposed paddle soldered to VEE
θJA = 28°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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Rev. PrA | Page 6 of 27

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ADN2816 pdf, datenblatt
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ADN2816
Preliminary Technical Data
JITTER SPECIFICATIONS
The ADN2816 CDR is designed to achieve the best bit-error-
rate (BER) performance and exceeds the jitter transfer, genera-
tion, and tolerance specifications proposed for SONET/SDH
equipment defined in the Telcordia Technologies specification.
0.1
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
ACCEPTABLE
RANGE
SLOPE = –20dB/DECADE
(UI), where 1 UI = 1 bit period. Jitter on the input data can
cause dynamic phase errors on the recovered clock sampling
edge. Jitter on the recovered clock causes jitter on the
retimed data.
fC
The following sections briefly summarize the specifications of
JITTER FREQUENCY (kHz)
jitter generation, transfer, and tolerance in accordance with the
Figure 10. Jitter Transfer Curve
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
JITTER TOLERANCE
ADN2816 performance with respect to those specifications.
The jitter tolerance is defined as the peak-to-peak amplitude of
JITTER GENERATION
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For SONET devices, the jitter generated
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating
conditions (see Figure 11).
must be less than 0.01 UI rms, and must be less than 0.1 UIp-p.
15.00
JITTER TRANSFER
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The jitter transfer function is the ratio of the jitter on the output
SLOPE = –20dB/DECADE
signal to the jitter applied on the input signal versus the
frequency. This parameter measures the limited amount of the
jitter on an input signal that can be transferred to the output
1.50
signal (see Figure 10).
0.15
f0 f1 f2 f3
JITTER FREQUENCY (kHz)
f4
Figure 11. SONET Jitter Tolerance Mask
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Rev. PrA | Page 12 of 27

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