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PDF ADN2814 Data sheet ( Hoja de datos )
| Número de pieza | ADN2814 | |
| Descripción | Continuous Rate 12.3 Mb/s to 675 Mb/s Clock and Data Recovery IC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
Continuous Rate 12.3 Mb/s to 675 Mb/s Clock and
Data Recovery IC with Integrated Limiting Amp
ADN2814
FEATURES
PRODUCT DESCRIPTION
Serial data input: 12.3 Mb/s to 675 Mb/s
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 6 mV typical
Adjustable slice level: ±100 mV
Patented clock recovery architecture
Loss of signal (LOS) detect range: 3 mV to 15 mV
Independent slice level adjust and LOS detector
No reference clock required
Loss of lock indicator
I2C™ interface to access optional features
Single-supply operation: 3.3 V
The ADN2814 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous
data rates from 12.3 Mb/s to 675 Mb/s. The ADN2814
automatically locks to all data rates without the need for an
external reference clock or programming. All SONET jitter
requirements are met, including jitter transfer, jitter generation,
and jitter tolerance. All specifications are quoted for −40°C to
+85°C ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.
Low power: 350 mW typical
5 mm × 5 mm 32-lead LFCSP, Pb Free
The receiver front end loss of signal (LOS) detector circuit
indicates when the input signal level has fallen below a user-
APPLICATIONS
SONET OC-1/3/12 and all associated FEC rates
ESCON, Fast Ethernet, Serial Digital Interface (DTV)
WDM transponders
adjustable threshold. The LOS detect circuit has hysteresis to
prevent chatter at the output.
The ADN2814 is available in a compact 5 mm × 5 mm 32-lead
chip scale package.
Regenerators/repeaters
Test equipment
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Broadband cross-connects and routers
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/N
(OPTIONAL)
LOL
CF1
CF2 VCC VEE
SLICEP/N
PIN
NIN
2
QUANTIZER
FREQUENCY
DETECT
LOOP
FILTER
PHASE
SHIFTER
PHASE
DETECT
LOOP
FILTER
VREF
LOS
DETECT
DATA
RE-TIMING
2
2
THRADJ
LOS DATAOUTP/N CLKOUTP/N
Figure 1.
VCO
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
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Preliminary Technical Data
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
Conditions
LVDS OUPUT CHARACTERISTICS
(CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing
Differential Output Swing
Output Offset Voltage
VSE (see Figure 3)
VDIFF (see Figure 3)
Output Impedance
Differential
LVDS Ouputs Timing
Rise Time
20% to 80%
Fall Time
80% to 20%
Setup Time
Hold Time
I2C INTERFACE DC CHARACTERISTICS
TS (see Figure 2), OC12
TH (see Figure 2), OC12
LVCMOS
Input High Voltage
VIH
Input Low Voltage
VIL
Input Current
Output Low Voltage
I2C INTERFACE TIMING
VIN = 0.1 VCC or VIN = 0.9 VCC
VOL, IOL = 3.0 mA
(See Figure 10)
SCK Clock Frequency
SCK Pulse Width High
SCK Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
tHIGH
tLOW
tHD;STA
tSU;STA
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Data Hold Time
tHD;DAT
SCK/SDA Rise/Fall Time
Stop Condition Setup Time
Bus Free Time between a Stop and a Start
TR/TF
tSU;STO
tBUF
REFCLK CHARACTERISTICS
Optional lock to REFCLK mode
Input Voltage Range
@ REFCLKP or REFCLKN
Minimum Differential Input Drive
VIL
VIH
Reference Frequency
Required Accuracy
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
VIH
Input Low Voltage
Input High Current
Input Low Current
VIL
IIH, VIN = 2.4 V
IIL, VIN = 0.4 V
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
VOH, IOH = −2.0 mA
VOL, IOL = 2.0 mA
Min
250
500
1125
0.7 VCC
−10.0
600
1300
600
600
100
300
20 + 0.1 Cb1
600
1300
12.3
2.0
−5
2.4
Typ
1200
100
TBD
TBD
800
800
0
VCC
100
100
1 Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed.
ADN2814
Max Unit
400
800
1275
0.3 VCC
+10.0
0.4
400
300
mV
mV
mV
Ω
ps
ps
ps
ps
V
V
µA
V
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
mV p-p
200 MHz
ppm
V
0.8 V
5 µA
µA
V
0.4 V
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Rev. PrA | Page 5 of 28
5 Page 
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Preliminary Technical Data
ADN2814
Table 6. Internal Register Map1
Reg Name R/W Address
FREQ0
R
0x0
FREQ1
R
0x1
FREQ2
R
0x2
RATE R 0x3
MISC R 0x4
CTRLA
W
0x8
CTRLB
W
0x9
CTRLC W 0x11
D7 D6
MSB
MSB
0 MSB
COARSE_RD[8] MSB
xx
D5
LOS
status
FREF range
Config Reset
LOL MISC[4]
00
System
reset
0
D4 D3
D2
Coarse datarate readback
Static
LOL
LOL
status
Datarate
measure
complete
Datarate/DIV_FREF ratio
0
Reset
MISC[2]
0
0 0 Config LOS
1 All writeable registers default to 0x00.
D1 D0
LSB
LSB
LSB
COARSE_RD[1]
x
COARSE_
RD[0] LSB
Measure
datarate
Lock to
reference
00
Squelch
mode
0
Table 7. Miscellaneous Register, MISC
LOS Status
D7 D6 D5
x x 0 = No loss of signal
1 = Loss of signal
Static LOL
D4
0 = Waiting for next LOL
1 = Static LOL until reset
LOL Status
D3
0 = Locked
1 = Acquiring
Datarate Measurement
Complete
D2
0 = Measuring datarate
1 = Measurement complete
D1
x
Coarse Rate
Readback LSB
D0
COARSE_RD[0]
Table 8. Control Register, CTRLA1
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FREF Range
Datarate/Div_FREF Ratio
Measure Datarate
D7 D6
D5 D4 D3 D2
D1
0 0 12.3 MHz to 25 MHz 0 0 0 0 1
Set to 1 to measure datarate
0 1 25 MHz to 50 MHz
00012
1 0 50 MHz to 100 MHz 0 0 1 0 4
1 1 100 MHz to 200 MHz
n 2n
1 0 0 0 256
Lock to Reference
D0
0 = Lock to input data
1 = Lock to reference clock
1 Where DIV_FREF is the divided down reference referred to the 12.3 MHz to 25 MHz band (see the Reference Clock (Optional) section).
Table 9. Control Register, CTRLB
Config LOL
Reset MISC[4]
System Reset
Reset MISC[2]
D7 D6 D5 D4 D3 D2 D1 D0
0 = LOL pin normal operation Write a 1 followed by Write a 1 followed by Set Write a 1 followed by Set Set Set
1 = LOL pin is static LOL
0 to reset MISC[4]
0 to reset ADN2814 to 0 0 to reset MISC[2]
to 0 to 0 to 0
Table 10. Control Register, CTRLC
D7
Set to 0
D6
Set to 0
D5
Set to 0
D4
Set to 0
D3
Set to 0
Config LOS
D2
0 = Active high LOS
1 = Active low LOS
Squelch Mode
D1
0 = Squelch CLK and DATA
1 = Squelch CLK or DATA
D0
Set to 0
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Rev. PrA | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADN2814.PDF ] | |
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