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PDF CY7C344 Data sheet ( Hoja de datos )
| Número de pieza | CY7C344 | |
| Descripción | 32-Macrocell MAX EPLD | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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44B
CY7C344
32-Macrocell MAX® EPLD
Features
• High-performance, high-density replacement for TTL,
74HC, and custom logic
• 32 macrocells, 64 expander product terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• 0.8-micron double-metal CMOS EPROM technology
• 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC
package
Functional Description
Available in a 28-pin, 300-mil DIP or windowed J-leaded ce-
ramic chip carrier (HLCC), the CY7C344 represents the dens-
est EPLD of this size. Eight dedicated inputs and 16 bidirec-
tional I/O pins communicate to one logic array block. In the
CY7C344 LAB there are 32 macrocells and 64 expander prod-
uct terms. When an I/O macrocell is used as an input, two
expanders are used to create an input path. Even if all of the
I/O pins are driven by macrocell registers, there are still 16
“buried” registers available. All inputs, macrocells, and I/O pins
are interconnected within the LAB.
The speed and density of the CY7C344 makes it a natural for
all types of applications. With just this one device, the designer
can implement complex state machines, registered logic, and
combinatorial “glue” logic, without using multiple chips. This
architectural flexibility allows the CY7C344 to replace multi-
chip TTL solutions, whether they are synchronous, asynchro-
nous, combinatorial, or all three.
Logic Block Diagram[1]
15(22)
15(23)
27(6)
28(7)
INPUT
INPUT
INPUT
INPUT
INPUT
1(8)
INPUT/CLK 2(9)
INPUT
13(20)
INPUT
14(21)
Pin Configurations
HLCC
Top View
4 3 2 1 28 27 26
MACROCELL 2
MACROCELL 1
I/O 3(10)
MACROCELL 4
MACROCELL 3
I/O 4(11)
MACROCELL 6 G MACROCELL 5 I
I/O 5(12)
MACROCELL 8
L
MACROCELL 7
O
I/O 6(13)
MACROCELL 10
O
MACROCELL 9DataSheet4U.com I/O 9(16)
MACROCELL 12
MACROCELL 14
MACROCELL 16
B
A
L
MACROCELL 11
MACROCELL 13
MACROCELL 15
C
O
N
I/O 10(17)
I/O 11(18)
I/O 12(19)
MACROCELL 18
MACROCELL 20
MACROCELL 22
B
U
S
MACROCELL 17
MACROCELL 19
MACROCELL 21
T
R
O
L
MACROCELL 24
MACROCELL 23
I/O 17(24)
I/O 18(25)
I/O 19(26)
I/O 20(27)
MACROCELL 26
MACROCELL 25
I/O 23(2)
MACROCELL 28
MACROCELL 27
I/O 24(3)
MACROCELL 30
MACROCELL 29
I/O 25(4)
MACROCELL 32
MACROCELL 31
I/O 26(5)
64 EXPANDER PRODUCT TERM ARRAY
32
C344–1
I/O
INPUT
INPUT
INPUT
INPUT/CLK
I/O
I/O
5 25
6 24
7 23
8 22
9 21
10 20
11
12 13 14 1516
1718 19
I/O
I/O
INPUT
INPUT
INPUT
INPUT
I/O
C344–2
CerDIP
Top View
INPUT
INPUT/CLK
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 INPUT
27 INPUT
26 I/O
25 I/O
24 I/O
23 I/O
22 VCC
21 GND
20 I/O
19 I/O
18 I/O
17 I/O
16 INPUT
15 INPUT
C344–3
Selection Guide
7C344-15
7C344-20
7C344-25
Maximum Access Time (ns)
15 20 25
Maximum Operating Current
(mA)
Commercial
Military
200 200 200
220 220
Industrial
220 220 220
Maximum Standby Current
(mA)
Commercial
Military
150 150 150
170 170
Industrial
170 170 170
Note:
DataSheet4U.1c. omNumbers in () refer to J-leaded packages.
DataShee
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-03006 Rev. **
Revised July 18, 2000
1 page  
www.DataSheet4U.com
CY7C344
et4U.com
External Synchronous Switching Characteristics[7] Over Operating Range (continued)
7C344-15 7C344-20 7C344-25
Parameter
Description
fMAX1
External Maximum Frequency(1/(tCO1 + tS))[4, 14]
Com’l/Ind
Mil
Min.
50.0
50.0
Max.
Min.
41.6
41.6
Max.
Min.
33.3
33.3
Max.
Unit
MHz
fMAX2
Maximum Frequency with Internal Only
Feedback (1/(tCF + tS))[4, 15]
Com’l/Ind 71.4
Mil 71.4
62.5
62.5
45.4 MHz
45.4
fMAX3
Data Path Maximum Frequency, least of
1/(tWL + tWH), 1/(tS + tH), or (1/tCO1)[4, 16]
Com’l/Ind 83.3
Mil 83.3
71.4
71.4
62.5
62.5
MHz
fMAX4
Maximum Register Toggle Frequency
1/(tWL + tWH)[4, 17]
Com’l/Ind 83.3 71.4 62.5 MHz
Mil 83.3 71.4 62.5
tOH
Output Data Stable Time from Synchronous
Clock Input[4, 18]
Com’l/Ind
Mil
3
3
3
3
3 ns
3
Notes:
8. This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander
terms are used to form the logic function.
9. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes
expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter
is tested periodically by sampling production material.
11. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used
to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output
for which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the
register is synchronously clocked. This parameter is tested periodically by sampling production material.
13. This specification is a measure of the delay associated with the internal register feedback path. This delay plus the register set-up time, tS, is the minimum
internal period for an internal state machine configuration. This parameter is tested periodically by sampling production material.
14. This specification indicates the guaranteed maximum frequencDyaattawShichheaestta4teUm.caochmine configuration with external only feedback can operate.
15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states
must also control external points, this frequency can still be observed as long as it is less than 1/tCO1. This specification assumes no expander logic is used. This
parameter is tested periodically by sampling production material.
16. This frequency indicates the maximum frequency at which the device may operate in data-path mode (dedicated input pin to output pin). This assumes that
no expander logic is used.
17. This specification indicates the guaranteed maximum frequency in synchronous mode, at which an individual output or buried register can be cycled by a
clock signal applied to either a dedicated input pin or an I/O pin.
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
DataShee
DataSheet4U.com
Document #: 38-03006 Rev. **
Page 5 of 15
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CY7C344
Switching Waveforms (continued)
Internal Synchronous (Output Path)
CLOCK FROM
LOGIC ARRAY
tRD
tOD
DATA FROM
LOGIC ARRAY
OUTPUT PIN
et4U.com
Ordering Information
Speed
(ns)
15
20
25
Ordering Code
CY7C344-15HC/HI
CY7C344-15JC/JI
CY7C344-15PC/PI
CY7C344-15WC/WI
CY7C344-20HC/HI
CY7C344-20JC/JI
CY7C344-20PC/PI
CY7C344-20WC/WI
CY7C344-20HMB
CY7C344-20WMB
CY7C344-25HC/HI
CY7C344-25JC/JI
CY7C344-25PC/PI
CY7C344-25WC/WI
CY7C344-25HMB
CY7C344-25WMB
tXZ tZX
HIGH Z
C344–14
Package
Name
H64
J64
P21
W22
H64
J64
P21
W22
H64
W22
H64
J64
P21
W22
H64
W22
Package Type
28-Lead Windowed Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Windowed CerDIP
D2a8-tLaeSahdeWeti4nUdo.wcoemd Leaded Chip Carrier
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier
28-Lead Windowed CerDIP
Operating
Range
Commercial/Industrial
Commercial/Industrial
Military
Commercial/Industrial
Military
DataShee
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIH
VIL
IIX
IOZ
ICC1
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Switching Characteristics
Parameter
tPD1
tPD2
tPD3
tCO1
tS
tH
tACO1
tACO1
tAS
tAH
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
MAX is a registered trademark of Altera Corporation.
Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor.
DataSheet4U.com
Document #: 38-03006 Rev. **
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CY7C344.PDF ] | |
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