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Teilenummer | WM8766 |
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Beschreibung | 24 BIT 192KHZ 6 CHANNEL DAC | |
Hersteller | Wolfson Microelectronics | |
Logo | ||
Gesamt 30 Seiten w
24-bit, 192kHz 6-Channel DAC
WM8766
DESCRIPTION
The WM8766 is a multi-channel audio DAC ideal for DVD
and surround sound processing applications for home hi-fi,
automotive and other audio visual equipment.
Three stereo 24-bit multi-bit sigma delta DACs are used
with oversampling digital interpolation filters. Digital audio
input word lengths from 16-32 bits and sampling rates from
8kHz to 192kHz are supported. Each DAC channel has
independent digital volume and mute control.
The audio data interface supports I2S, left justified, right
justified and DSP digital audio formats
The device is controlled via a 3 wire serial interface or
directly using the hardware interface. These interfaces
provide access to features including channel selection,
volume controls, mutes, de-emphasis and power
management facilities. The device is available in a 28-lead
SSOP.
BLOCK DIAGRAM
FEATURES
• 6-Channel DAC
• Audio Performance
− 103dB SNR (‘A’ weighted @ 48kHz) DAC
• DAC Sampling Frequency: 8kHz – 192kHz
• 3-Wire SPI Serial or Hardware Control Interface
• Programmable Audio Data Interface Modes
− I2S, Left, Right Justified or DSP
− 16/20/24/32 bit Word Lengths
• Three Independent stereo DAC outputs with independent
digital volume controls
• Master or Slave Audio Data Interface
• 2.7V to 5.5V Analogue, 2.7V to 3.6V Digital supply
Operation
• 28 lead SSOP Package
APPLICATIONS
• DVD Players
• Surround Sound AV Processors and Hi-Fi systems
• Automotive Audio
WOLFSON MICROELECTRONICS plc
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Production Data, July 2005, 4.1
Copyright 2005 Wolfson Microelectronics plc
WM8766
Production Data
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX
Digital supply range
DVDD
2.7 3.6
Analogue supply range
AVDD, VREFP
2.7 5.5
Ground
AGND, VREFN, DGND
0
Difference DGND to AGND
-0.3 0 +0.3
Note: Digital supply DVDD must never be more than 0.3V greater than AVDD for normal operation of the device .
UNIT
V
V
V
V
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP MAX
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
0.3 x DVDD
Input HIGH level
Output LOW
Output HIGH
Analogue Reference Levels
VIH
VOL
VOH
IOL=1mA
IOH= -1mA
0.7 x DVDD
0.9 x DVDD
0.1 x DVDD
Reference Voltage
VVMID
VREFP/2
Potential Divider Resistance
RVMID
(VREFP to VMID) and
(VMID to VREFN)
133
DAC Performance (Load = 10kΩ, 50pF)
0dBFs Full Scale Output
Voltage
1.0 x
VREFP/5
SNR (Note 1,2,4)
A-weighted,
95 103
@ fs = 48kHz
SNR (Note 1,2,4)
A-weighted
101
@ fs = 96kHz
SNR (Note 1,2,4)
A-weighted
101
@ fs = 192kHz
SNR (Note 1,2,4)
A-weighted
101
@ fs = 48kHz, AVDD =
3.3V
SNR (Note 1,2,4)
A-weighted
99
@ fs = 96kHz, AVDD =
3.3V
Dynamic Range (Note 2,4)
DNR
A-weighted, -60dB full
scale input
95
103
Total Harmonic Distortion (THD)
1kHz, 0dBFs
-90 -80
Mute Attenuation
1kHz Input, 0dB gain
100
DAC Channel Separation
100
Power Supply Rejection Ratio
PSRR
1kHz 100mVpp
50
20Hz to 20kHz
100mVp-p
45
Supply Current
Analogue Supply Current
AVDD, VREFP = 5V
13.8
Digital Supply Current
DVDD = 3.3V
11.0
UNIT
V
V
V
V
V
kΩ
Vrms
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
mA
mA
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PD Rev 4.1 July 2005
6
6 Page WM8766
Production Data
DEVICE DESCRIPTION
INTRODUCTION
WM8766 is a complete 6-channel DAC including digital interpolation and decimation filters and
switched capacitor multi-bit sigma delta DACs with digital volume controls on each channel and
output smoothing filters.
The device is implemented as 3 separate stereo DACs in a single package and controlled by a single
interface.
Each stereo DAC has its own data input DIN1/2/3. DAC word clock LRCLK, DAC bit clock BCLK and
DAC master clock MCLK are shared between them.
The Audio Interface may be configured to operate in either master or slave mode. In Slave mode,
LRCLK and BCLK are all inputs. In Master mode, LRCLK and BCLK are all outputs.
Each DAC has its own digital volume control that is adjustable in 0.5dB steps. The digital volume
controls may be operated independently. In addition, a zero cross detect circuit is provided for each
DAC for the digital volume controls. The digital volume control detects a transition through the zero
point before updating the volume. This minimises audible clicks and ‘zipper’ noise as the gain values
change.
Control of internal functionality of the device is by 3-wire serial or pin programmable control interface.
The software control interface may be asynchronous to the audio data interface as control data will
be re-synchronised to the audio processing internally.
Operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided for the DAC.
In Slave mode selection between clock rates is automatically controlled. In master mode, the sample
rate is set by control bit DACRATE. Audio sample rates (fs) from less than 8ks/s up to 192ks/s are
allowed for the DAC, provided the appropriate master clock is input.
The audio data interface supports right justified, left justified and I2S interface formats along with a
highly flexible DSP serial port interface.
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. The external master system clock can be applied directly through the DAC MCLK input
pin(s) with no software configuration necessary.
The DAC master clock for WM8766 supports audio sampling rates from 128fs to 768fs, where fs is
the audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
In Slave mode the WM8766 has a master clock detection circuit that automatically determines the
relationship between the system clock frequency and the sampling rate (to within +/- 32 master
clocks). If there is a greater than 32 clocks error the interface defaults to 768fs mode. The WM8766
is tolerant of phase variations or jitter on the master clock. Table 6 shows the typical master clock
frequency inputs for the WM8766.
The signal processing for the WM8766 typically operates at an oversampling rate of 128fs. The
exception to this is for operation with a 128/192fs system clock, e.g. for 192kHz operation, when the
oversampling rate is 64fs.
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PD Rev 4.1 July 2005
12
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ WM8766 Schematic.PDF ] |
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