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DP83956A Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DP83956A
Beschreibung (DP83955A / DP83956A) LitE Repeater Interface Controller
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 30 Seiten
DP83956A Datasheet, Funktion
www.DataSheet4U.com
July 1993
DP83955A DP83956A LERICTM
LitE Repeater Interface Controller
General Description
The DP83955 56 LitE Repeater Interface Controller Specifications enclosed describe both the DP83955 and the
(LERIC) may be used to implement an IEEE 802 3 multiport DP83956 unless otherwise noted
repeater unit It fully satisfies the IEEE 802 3 repeater speci-
fication including the functions defined by the repeater seg-
ment partition and jabber lockup protection state machines
For IEEE 802 3 multiport repeater applications which re-
quire conformance to the IEEE 802 3 Draft Repeater Man-
agement options the DP83950 Repeater Interface Control-
The LERIC has an on-chip phase-locked-loop (PLL) for ler (RICTM) is recommended especially for highly-managed
Manchester data decoding a Manchester encoder and an hub requirements
Elasticity Buffer for preamble regeneration
Each LERIC can connect up to 7 cable segments via its Features
network interface ports One port is fully Attachment Unit Y Compliant with the IEEE 802 3 Repeater Specification
Interface (AUI) compatible and is able to connect to an ex- Y 7 network connections (ports) per chip
ternal Medium Attachment Unit (MAU) using the maximum
length of AUI cable The other 6 ports have integrated
10BASE-T transceivers These transceiver functions may
be bypassed so that the LERIC may be used with external
transceivers such as National’s DP8392 coaxial transceiv-
er In addition large repeater units may be constructed by
cascading LERICs together over the Inter-LERICTM or Inter-
RICTM bus
Y Selectable on-chip twisted-pair transceivers
Y Cascadable for large multiple RIC LERIC hub
applications
Y Compatible with AUI compliant transceivers
Y On-chip Elasticity Buffer Manchester encoder and
decoder
Y Separation Partition state machines for each port
The LERIC is configurable for specific applications It pro- Y Provides port status information for LED displays
vides port status information for LED array displays Addi-
including receive collision partition polarity and link
tionally the LERIC has a mP interface to provide individual
status
port status configuration and port enable disable func- Y Power-up configuration options Repeater and Partition
tions
Specifications Transceiver Interface Status Display
The
that
DP83956 has
two of the
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for
repeater
management
changed to unidirectional signals on DP83956 and one
and port disable
more signal is added to DP83956 to accommodate the addi- Y Per port receive squelch level selection
tion of bus transceivers for cascading a greater number of Y CMOS process for low power dissipation
LERICs in large repeater applications
Y Single 5V supply
1 0 System Diagram
Simple LERIC Hub
DataShee
TRI-STATE is a registered trademark of National Semiconductor Corporation
Inter-LERICTM Inter-RICTM LERICTM and RICTM are trademarks of National Semiconductor Corporation
PAL is a registered trademark of and used under license from Advanced Micro Devices Inc
GAL is a registered trademark of Lattice Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11240
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TL F 11240 – 1
RRD-B30M105 Printed in U S A






DP83956A Datasheet, Funktion
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et4U.com
2 0 Connection Diagrams (Continued)
Pin Name
TX4a
TX4b
GND
VCC
TX5b
TX5a
CD5b
CD5a
RX5b
RX5a
GND
VCC
RX6b
RX6a
CD6a
CD6b
TX6a
TX6b
GND
VCC
TX7b
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Pin Table for DP83955
(Configured as Port 1 Full AUI Ports 2 – 7 AUI)
Pin Name Pin No
Pin Name
Pin No
TX7a 22 RXM
43
CD7b 23 IRD
44
CD7a 24 IRC
45
RX7b 25 STR
46
RX7a 26 DFS
47
GND
27
BUFEN
48
VCC 28 ACKO 49
IRE 29 CD1a 50
ACTN
30
CD1b
51
ANYXN
31
RX1a
52
COLN 32 RX1b 53
D7
33 VCC
54
D6
34 GND
55
D5 35 TX1a 56
D4 36 TX1b 57
D3
37 GND
58
D2
38 VCC
59
D1 39 RX2b 60
D0 40 RX2a 61
VCC 41 CD2a 62
GND 42 DataCSD2hbeet4U.com63
Pin Name
TX2a
TX2b
GND
VCC
TX3b
TX3a
CD3b
CD3a
RX3b
RX3a
GND
VCC
CLK
MLOAD
WR
RD
ACKI
RX4b
RX4a
CD4a
CD4b
Pin No
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DataShee
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6
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DP83956A pdf, datenblatt
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3 0 Pin Description (Continued)
Pin Driver I O
Name Type
Description
PROCESSOR BUS PINS
STR
C O Display Update STRobe This signal controls the latching of display data for network ports into the off
chip display latches
During processor access cycles (read or write is asserted) this signal is inactive (high)
D(7 0)
TT B Z Data Bus
Display Update Cycles These pins become outputs providing display data and port address
information
Processor Access Cycles Address input D(7 4) and Data input or output D(3 0) is performed via these
pins The read write and reset inputs control the direction of the signals
Note The data pins remain in their display update function (i e asserted as outputs) unless either the read or write
strobe is asserted
DFS
C O Display Frozen Strobe The assertion of the DFS signal active high at the end of the transmission of
each packet indicates that the status of that packet is frozen on the LEDs until the beginning of the next
received packet or for a maximum of 30 ms
BUFEN
C
O BUFfer ENable This output controls the TRI-STATE operation of the bus transceiver which provides
the interface between the LERIC’s data pins and the processor’s data bus
Note The buffer enable output indicates the function of the data pins When it is high they are performing display update
cycles when it is low a processor access or MLOAD cycle is occurring
WR TT I WRite Strobe Strobe from the CPU used to write an internal register defined by the D(7 4) inputs
RD TT I ReaD Strobe Strobe from the CPU used to read an internal register defined by the D(7 4) inputs
MLOAD TT
I Device MLOAD and Reset When this input is low all of the RIC’s state machines and network ports are
reset and held inactive On the rising edge of MLOAD the logic levels present on the D(7 0) pins are
latched into the LERIC’s configuration registers The rising edge of MLOAD also signals the beginning
of the display test operation
INTER-LERIC BUS PINS
ACKI
TT I ACKnowledge Input Input to the network ports’ arbitration chain
ACKO
IRD
TT O ACKnowledge Output Output from thDe naettawSorhk peoertts4’ aUrb.ictroatmion chain
TT B Z Inter-LERIC Data When asserted as an output this signal provides a serial data stream in NRZ format
The signal is asserted by a LERIC when it is receiving data from one of its network segments The
default condition of this signal is to be an input In this state it may be driven by other devices on the
Inter-LERIC bus
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