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PDF PC405GP3EE266C Data sheet ( Hoja de datos )
| Número de pieza | PC405GP3EE266C | |
| Descripción | Power PC Embedded Processor | |
| Fabricantes | Applied Micro Circuits | |
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405GP
Power PC 405GP Embedded Processor
Part Number 405GP
Revision 2.01 – January 6, 2005
Data Sheet
Features
• PowerPC® 405 32-bit RISC processor core
operating up to 266MHz
• Synchronous DRAM (SDRAM) interface operating
up to 133MHz
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
• PCI Revision 2.2 compliant interface (32-bit, up to
66 MHz)
- Synchronous or asynchronous PCI Bus
interface
- Internal or external PCI Bus Arbiter
• Ethernet 10/100Mbps (full-duplex) support with
media independent interface (MII)
• 4KB on-chip memory (OCM)
• External peripheral bus
• Programmable interrupt controller supports seven
external and 19 internal edge triggered or level-
sensitive interrupts
- Flash ROM/Boot ROM interface
• Programmable timers
- Direct support for 8-, 16-, or 32-bit SRAM and
external peripherals
- Up to eight devices
• Two serial ports (16550 compatible UART)
• One IIC interface
- External Mastering supported
DataSheet4U•.coGmeneral purpose I/O (GPIO) available
• DMA support for external peripherals, internal
UART and memory
- Scatter-gather chaining supported
• Supports JTAG for board level testing
• Internal processor local Bus (PLB) runs at SDRAM
interface frequency
- Four channels
• Supports PowerPC processor boot from PCI
memory
DataShee
Description
Designed specifically to address embedded
applications, the PowerPC 405GP (PPC405GP)
provides a high-performance, low-power solution that
interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation requirements.
This chip contains a high-performance RISC
processor core, SDRAM controller, PCI bus interface,
Ethernet interface, control for external ROM and
peripherals, DMA with scatter-gather support, serial
ports, IIC interface, and general purpose I/O.
Technology: CMOS SA-12E, 0.25 µm
(0.18 µm Leff)
Package: 456-ball (35mm or 27mm), or 413-ball
(25mm) enhanced plastic ball grid array (E-PBGA)
Power (typical): TBDW at 133MHz, 1.5W at 200MHz,
2W at 266MHz
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Revision 2.01 – January 6, 2005
Data Sheet
405GP – Power PC 405GP Embedded Processor
Order Part Number Key
PPC405GP-3BE266Cx
Part Number
Grade 3 Reliability
Package
B: 35mm, 456 E-PBGA
D: 27mm, 456 E-PBGA
E: 25mm, 413 E-PBGA
F: 35mm, 456 E-PBGA lead-free
K: 27mm, 456 E-PBGA lead-free
Shipping Package
Blank = Tray
Z = Tape and reel
Operational Case Temperature
Range (-40°C to +85°C)
Processor Speed
133 MHz
200 MHz
266 MHz
Revision Level
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Revision 2.01 – January 6, 2005
Data Sheet
405GP – Power PC 405GP Embedded Processor
• Peripheral Device pacing with external “Ready”
• External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
DMA Controller
• Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
- Buffered memory to peripheral transfers
• Four channels
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• Scatter/gather capability for programming multiple DMA operations
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 32-bit addressing
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• Address increment or decrement
• Internal 32-byte data buffering capability
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses
Serial Interface
• One 8-pin UART and one 4-pin UART interface provided
• Selectable internal or external serial clock to allow a wide range of baud rates
• Register compatibility with NS16550 register set
• Complete status reporting capability
• Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA engine
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