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A1240A Schematic ( PDF Datasheet ) - Actel

Teilenummer A1240A
Beschreibung (A1225A - A1280A) FPGAs
Hersteller Actel
Logo Actel Logo 




Gesamt 30 Seiten
A1240A Datasheet, Funktion
www.DataSheet4U.com
v4.0.1
ACT2 Family FPGAs
Features
Up to 8000 Gate Array Gates
(20,000 PLD equivalent gates)
Replaces up to 200 TTL Packages
Replaces up to eighty 20-Pin PAL® Packages
Design Library with over 500 Macro Functions
Single-Module Sequential Functions
Wide-Input Combinatorial Functions
Up to 1232 Programmable Logic Modules
Up to 998 Flip-Flops
Datapath Performance at 105 MHz
16-Bit Accumulator Performance to 39 MHz
Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz
Two High-Speed, Low-Skew Clock Networks
I/O Drive to 10 mA
Nonvolatile, User Programmable
Logic Fully Tested Prior to Shipment
1.0-micron CMOS Technology
Product Family Profile
Device
A1225A
A1240A
A1280A
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
2,500
6,250
DataSheet46U3.com
25
4,000
10,000
100
40
8,000
20,000
200
80
DataShee
Logic Modules
S-Modules
C-Modules
451 684 1,232
231 348 624
220 336 608
Flip-Flops (maximum)
382 568 998
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Channel
PLICE Antifuse Elements
36
15
250,000
36
15
400,000
36
15
750,000
User I/Os (maximum)
Packages1
Performance2
16-Bit Prescaled Counters
16-Bit Loadable Counters
16-Bit Accumulators
83
100 CPGA
100 PQFP
100 VQFP
84 PLCC
105 MHz
70 MHz
39 MHz
104
132 CPGA
144 PQFP
176 TQFP
84 PLCC
100 MHz
69 MHz
38 MHz
140
176 CPGA
160 PQFP
176 TQFP
84 PLCC
172 CQFP
85 MHz
67 MHz
36 MHz
Notes:
1. See the “Product Plan” on page 3 for package availability.
2. Performance is based on ‘–2’ speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1, Version 1.2,
dated 3-28-93, any analysis is not endorsed by PREP.
DataSheet4U.com
December 2000
DataSheet 4 U .c©o2m000 Actel Corporation
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A1240A Datasheet, Funktion
www.DataSheet4U.com
ACT2 Family FPGAs
and load device inputs. An additional component of the
active power dissipation is the totem-pole current in CMOS
transistor pairs. The net effect can be associated with an
equivalent capacitance that can be combined with
frequency and voltage to represent active power dissipation.
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
the Equation 1.
Power (µW) = CEQ * VCC2 * F
(1)
Where:
CEQ is the equivalent capacitance expressed in pF.
VCC is the power supply in volts.
F is the switching frequency in MHz.
Equivalent capacitance is calculated by measuring ICC
r2 = Fixed capacitance due to second routed array
clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in
pF
CL = Output lead capacitance in pF
fm = Average logic module switching rate in MHz
fn = Average input buffer switching rate in MHz
fp = Average output buffer switching rate in MHz
fq1 = Average first routed array clock rate in MHz
fq2 = Average second routed array clock rate in MHz
active at a specified frequency and voltage for each circuit
Fixed Capacitance Values for Actel FPGAs
component of interest. Measurements have been made over (pF)
a range of frequencies at a fixed value of VCC. Equivalent
capacitance is frequency independent so that the results
Device Type
r1
routed_Clk1
r2
routed_Clk2
may be used over a wide range of operating conditions.
A1225A
106
106.0
Equivalent capacitance values are shown below.
et4U.com CEQ Va lues f or Ac tel F PGA s
Modules (CEQM)
5.8
Input Buffers (CEQI)
12.9
A1240A
A1280A
134
168
134.2
167.8
Determining Average Switching Frequency
DataSheTeot4dUet.ecrommine the switching frequency for a design, you must
have a detailed understanding of the data input values to
Output Buffers (CEQO)
23.8
Routed Array Clock Buffer Loads (CEQCR)
3.9
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic
the circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
must be known. Equation 2 shows a piece-wise linear
summation over all components.
Power = VCC2 * [(m * CEQM* fm)modules +(n * CEQI* fn)inputs
+ (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR *
fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR *
fq2)routed_Clk2
+ (r2 * fq2)routed_Clk2]
(2)
Where:
Logic Modules (m)
Inputs switching (n)
Outputs switching (p)
First routed array clock loads (q1)
Second routed array clock loads (q2)
80% of modules
# inputs/4
# outputs/4
40%of
sequential
modules
40%of
sequential
m = Number of logic modules switching at fm
modules
n = Number of input buffers switching at fn
p = Number of output buffers switching at fp
q1 = Number of clock loads on the first routed array
clock
q2 = Number of clock loads on the second routed
array clock
r1 = Fixed capacitance due to first routed array
clock
DataSheet4U.com
Load capacitance (CL)
35 pF
Average logic module switching rate (fm) F/10
Average input switching rate (fn)
F/5
Average output switching rate (fp)
F/10
Average first routed array clock rate (fq1) F
Average second routed array clock rate F/2
(fq2)
DataShee
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A1240A pdf, datenblatt
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ACT2 Family FPGAs
A1225A Timing Characteristics
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
Logic Module Propagation Delays1
‘–2Speed
‘–1Speed
StdSpeed
Parameter Description
Min. Max. Min. Max. Min. Max. Units
tPD1 Single Module
tCO Sequential Clk to Q
tGO Latch G to Q
tRS Flip-Flop (Latch) Reset to Q
Predicted Routing Delays2
3.8 4.3 5.0 ns
3.8 4.3 5.0 ns
3.8 4.3 5.0 ns
3.8 4.3 5.0 ns
tRD1 FO=1 Routing Delay
tRD2 FO=2 Routing Delay
tRD3 FO=3 Routing Delay
tRD4 FO=4 Routing Delay
tRD8 FO=8 Routing Delay
Sequential Timing Characteristics3,4
1.1 1.2 1.4 ns
1.7 1.9 2.2 ns
2.3 2.6 3.0 ns
2.8 3.1 3.7 ns
4.4 4.9 5.8 ns
tSUD
Flip-Flop (Latch) Data Input
Setup
0.4
0.4
0.5
ns
tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 0.0 ns
et4U.com tSUENA
Flip-Flop (Latch) Enable Setup
0.8
0.9
1.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
DataSheet4U.com
4.5 5.0
6.0
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.5
5.0
6.0
ns
tA
tINH
tINSU
tOUTH
tOUTSU
fMAX
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
Flip-Flop (Latch) Clock
Frequency
9.4 11.0 13.0 ns
0.0 0.0 0.0 ns
0.4 0.4 0.5 ns
0.0 0.0 0.0 ns
0.4 0.4 0.5 ns
105.0
90.0
75.0 MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
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