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PDF EDS1216AABH Data sheet ( Hoja de datos )
| Número de pieza | EDS1216AABH | |
| Descripción | (EDS1216AABH / EDS1216CABH) 128M bits SDRAM (8M words x 16 bits) | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
128M bits SDRAM
EDS1216AABH, EDS1216CABH
(8M words × 16 bits)
Description
The EDS1216AABH, EDS1216CABH are 128M bits
SDRAM organized as 2,097,152 words × 16 bits × 4
banks. All inputs and outputs are synchronized with
the positive edge of the clock.
Supply voltages are 3.3V (EDS1216AABH) and 2.5V
(EDS1216CABH).
They are packaged in 54-ball FBGA.
Features
• 3.3V and 2.5V power supply
• Clock frequency: 133MHz (max.)
• Single pulsed /RAS
• ×16 organization
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single
write operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by UDQM and LDQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
• FBGA package with lead free solder (Sn-Ag-Cu)
Pin Configurations
/xxx indicate active low signal.
54-ball FBGA
123456789
A
VSS DQ15 VSSQ
B
DQ14 DQ13 VDDQ
C
DQ12 DQ11 VSSQ
D
DQ10 DQ9 VDDQ
E
DQ8 NC VSS
F
UDQM CLK CKE
G
NC A11 A9
H
A8 A7 A6
J
VSS A5 A4
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD LDQM DQ7
/CAS /RAS /WE
BA0 BA1 /CS
A0 A1 A10
A3 A2 VDD
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
CLK
CKE
/CS
/RAS
/CAS
/WE
LDQM /UDQM
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select
Data inputs/ outputs
Clock input
Clock enable
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Power supply
Ground
Power supply for DQ
Ground for DQ
No connection
Document No. E0410E40 (Ver. 4.0)
Date Published February 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
DataSheet4 U .com
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Elpida Memory, Inc. 2003-2005
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EDS1216AABH, EDS1216CABH
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS1216AA]
(TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS1216CA]
EDS1216AA EDS1216CA
Parameter
Symbol
Operating current
IDD1
Standby current in power
down
IDD2P
Standby current in power
down (input signal stable)
IDD2PS
Standby current in non power
down
IDD2N
Standby current in non power
down (input signal stable)
IDD2NS
Active standby current in
power down
IDD3P
Active standby current in
power down (input signal
IDD3PS
stable)
Active standby current in non
power down
IDD3N
Active standby current in non
power down (input signal
IDD3NS
stable)
Burst operating current
IDD4
Grade
max.
100
3
2
20
9
4
3
40
25
120
max.
100
3
2
20
9
4
3
40
25
120
Unit Test condition
mA
Burst length = 1
tRC = tRC (min.)
mA
CKE = VIL,
tCK = tCK (min.)
Notes
1, 2, 3
6
mA CKE = VIL, tCK = ∞ 7
mA
CKE, /CS = VIH,
tCK = tCK (min.)
4
mA
CKE = VIH, tCK = ∞,
/CS = VIH
8
mA
CKE = VIL,
tCK = tCK (min.)
1, 2, 6
mA CKE = VIL, tCK = ∞ 2, 7
mA
CKE, /CS = VIH,
tCK = tCK (min.)
1, 2, 4
mA
CKE = VIH, tCK = ∞,
/CS = VIH
2, 8
mA
tCK = tCK (min.),
BL = 4
1, 2, 5
Refresh current
IDD5
220
220
mA tRC = tRC (min.)
3
Self refresh current
IDD6
1.5
1.5
mA
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Data Sheet E0410E40 (Ver. 4.0)
DataSheet4 U .com
5
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EDS1216AABH, EDS1216CABH
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends
operation.
When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode.
During power down mode, CKE must remain low.
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
A0 to A11 (input pins)
Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle.
Column Address is determined by A0 to A8 at the CLK rising edge in the read or write command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
Bank 0
L
Bank 1
H
Bank 2
L
Bank 3
H
Remark: H: VIH. L: VIL.
BA1
L
L
H
H
UDQM and LDQM (input pins)
UDQM and LDQM control input/output buffers. UDQM and LDQM control upper byte (DQ8 to DQ15) and lower byte
(DQ0 to DQ7).
DQ0 to DQ15 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0410E40 (Ver. 4.0)
DataSheet4 U .com
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| PDF Descargar | [ Datasheet EDS1216AABH.PDF ] | |
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