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PDF EP1810LC Data sheet ( Hoja de datos )
| Número de pieza | EP1810LC | |
| Descripción | EPLD Family | |
| Fabricantes | Altera | |
| Logotipo |  |
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www.DataSheet4U.com
May 1999, ver. 5
Features
Classic
® EPLD Family
Data Sheet
s Complete device family with logic densities of 300 to 900 usable gates
(see Table 1)
s Device erasure and reprogramming with non-volatile EPROM
configuration elements
s Fast pin-to-pin logic delays as low as 10 ns and counter frequencies
as high as 100 MHz
s 24 to 68 pins available in dual in-line package (DIP), plastic J-lead
chip carrier (PLCC), pin-grid array (PGA), and small-outline
integrated circuit (SOIC) packages
s Programmable security bit for protection of proprietary designs
s 100% generically tested to provide 100% programming yield
s Programmable registers providing D, T, JK, and SR flipflops with
individual clear and clock controls
s Software design support featuring the Altera® MAX+PLUS® II
development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000
workstations, and third-party development systems
s Programming support with Altera’s Master Programming Unit
(MPU); programming hardware from Data I/O, BP Microsystems,
and other third-party programming vendors
s Additional design entry and simulation support provided by EDIF,
library of parameterized modules (LPM), Verilog HDL, VHDL, and
other interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, and VeriBest
Table 1. Classic Device Features
Feature
Usable gates
Macrocells
Maximum user I/O pins
tPD (ns)
fCNT (MHz)
EP610
EP610I
300
16
22
10
100
EP910
EP910I
450
24
38
12
76.9
EP1810
900
48
64
20
50
Altera Corporation
A-DS-CLASSIC-05
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Classic EPLD Family Data Sheet
Figure 2. Classic Output Enable/Clock Select
Mode 0
In Mode 0, the register
is clocked by the global
clock signal. The
output is enabled by
the logic from the
product term.
AND
Array
Global
Clock
OE = Product Term
CLK = Global
VCC
Data
Output Enable/Clock
Select
OE
CLK
Q
Macrocell
CLR
Output Buffer
Mode 1
In Mode 1, the output
Global
Clock
is permanently enabled
and the register is
AND
Array
clocked by the product
term, which allows
gated clocks to be
generated.
OE = Enabled
CLK = Product Term
VCC
Data
Output Enable/Clock
Select
OE
CLK
Q
Macrocell
CLR
Output Buffer
Feedback Select
Each macrocell in a Classic device provides feedback selection that is
controlled by the feedback multiplexer. This feedback selection allows the
designer to feed either the macrocell output or the I/O pin input
associated with the macrocell back into the AND array. The macrocell
output can be either the Q output of the programmable register or the
combinatorial output of the macrocell. Different devices have different
feedback multiplexer configurations. See Figure 3.
Figure 3. Classic Feedback Multiplexer Configurations
Global Feedback Multiplexer
Global
Q
I/O
EP610
EP610I
EP910
EP910I
Quadrant Feedback Multiplexer
Quadrant
Q
I/O
EP1810
Dual Feedback Multiplexer
Quadrant
Global
Q
I/O
EP1810
Altera Corporation
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EP610 EPLD
Features
s High-performance, 16-macrocell Classic EPLD
– Combinatorial speeds with tPD as fast as 10 ns
– Counter frequencies of up to 100 MHz
– Pipelined data rates of up to 125 MHz
s Programmable I/O architecture with up to 20 inputs or 16 outputs
and 2 clock pins
s EP610 and EP610I devices are pin-, function-, and programming
file-compatible
s Programmable clock option for independent clocking of all registers
s Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
s Available in the following packages (see Figure 7):
– 24-pin small-outline integrated circuit (plastic SOIC only)
– 24-pin ceramic and plastic dual in-line package (CerDIP and
PDIP)
– 28-pin plastic J-lead chip carrier (PLCC)
Figure 7. EP610 Package Pin-Out Diagrams
Package outlines not drawn to scale. Windows in ceramic packages only.
CLK1
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 INPUT
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 INPUT
13 CLK2
CLK1
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 INPUT
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 INPUT
13 CLK2
4 3 2 1 28 27 26
I/O 5
25
I/O 6
24
I/O 7
23
I/O 8
I/O 9
EP610
22
21
I/O 10
20
NC 11
19
12 13 14 15 16 17 18
I/O
I/O
I/O
I/O
I/O
I/O
NC
24-Pin SOIC
EP610
24-Pin DIP
EP610
EP610I
28-Pin PLCC
EP610
EP610I
Altera Corporation
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