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DP83907 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DP83907
Beschreibung AT/LANTIC
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 70 Seiten
DP83907 Datasheet, Funktion
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PRELIMINARY
November 1995
DP83907 AT LANTICTMII
General Description
The DP83907 Twisted-Pair Enhanced Coaxial Network In-
terface Controller is a CMOS VLSI device designed for easy
implementation of CSMA CD local area networks
Unique to the DP83907 is the integration of the entire bus
interface for PCAT ISA (Industry Standard Architecture) bus
based systems Hardware and software selectable options
allow the DP83907’s bus interface to be configured in the
same manner as an NE2000 Architecture All bus drivers
and control logic are integrated to reduce board cost and
area
Supported network interfaces include 10BASE5 or
10BASE2 Ethernet via an external transceiver connected to
its AUl port and Twisted-pair Ethernet (10BASE-T) using
the on-board transceiver The DP83907 provides the Ether-
net Media Access Control (MAC) Encode-Decode (ENDEC)
with an AUl interface and 10BASE-T transceiver functions
in accordance with the lEEE 802 3 standards
The DP83907’s integrated 10BASE-T transceiver fully com-
plies with the IEEE standard This functional block incorpo-
rates the receiver transmitter collision heartbeat loop-
back jabber and link integrity blocks as defined in the stan-
dard The transceiver when combined with equalization re-
sistors transmit receive filters and pulse transformers pro-
vides a complete physical interface from the DP83907’s
ENDEC module and the twisted pair medium (continued)
Features
Y Controller and integrated bus interface solution for IEEE
802 3 10BASE5 10BASE2 and 10BASE-T
Y Software compatible with industry standard Ethernet
Adapters Novell ’s NE2000
Y No external bus logic or drivers needed
Y Supports jumpered or jumperless configuration
Y Provides EEPROM interface for non-volatile storage of
configuration data user-defined data and Ethernet
Physical Address
Y Allows in-situ programming of EEPROM
Y Integrated controller ENDEC and transceiver
Y Full IEEE 802 3 compliant AUI interface
Y Single 5V supply
10BASE-T TRANSCEIVER MODULE
Y Integrates transceiver functionality
Y Transmitter and receiver functions
Y Collision detect heartbeat and jabber
Y Selectable link integrity test or link disable
Y Polarity Detection Correction
Y Auto switch
Y On chip filter
ENDEC MODULE
Y 10 Mbit s Manchester encoding decoding
Y Squelch on receive and collision pairs
MAC CONTROLLER MODULE
Y Software compatible with DP8390 DP83901 DP83902
Y Efficient buffer management implementation
IN-CIRCUIT TEST
1 0 System Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
AT LANTICTM is a trademark of National Semiconductor Corporation
Ethernet is a registered trademark of Xerox Corporation
NetWareTM is a trademark of Novell Incorporated
Novell is a registered trademark of Novell Incorporated
C1995 National Semiconductor Corporation TL F 12082
TL F 12082 – 1
RRD-B30M115 Printed in U S A
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DP83907 Datasheet, Funktion
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2 0 Pin Description (Continued)
Pin No Pin Name
Type
Description
EXTERNAL MEMORY SUPPORT
87 – 94
MSD0 – 7 or
CA0 – 7 or
DO DI SK
I O–I–O
MOS
MEMORY SUPPORT DATA BUS CONFIGURATION REGISTER A INPUT EEPROM
SIGNALS
MSD0–7 When RESET is inactive these pins are used to access external memory and boot
PROM
CA0–7 When RESET is active Configuration Register A is loaded with the data value on
these pins If the user puts an external pull-up on any of these pins then the corresponding
register bit is set to a 1 If the pin is left unconnected then the register bit is 0
DO DI SK When RESET goes from an active to an inactive level DP83907 will read the
contents of a serial EEPROM using these signals and load the contents into internal
registers These internal registers are mapped into the space taken up by the PROM in the
NE2000 Architecture After the EEPROM read operation has completed these pins will revert
to MSD0 – 2 (D0 e MSD0 DI e MSD1 SK e MSD2)
77 – 82 MSD8 – 15 or
85 86 CB0 – 7
I O–I
MOS
MEMORY SUPPORT DATA BUS CONFIGURATION REGISTER B INPUT
MSD8–15 When RESET is inactive these pins are used to access external memory
CB0–7 When RESET is active Configuration Register B is loaded with the data value on
these pins If the user puts an external pull-up on any of these pins then the corresponding
register bit is set to a 1 If the pin is left unconnected then the register bit is 0
60 – 67 MSA1 – 8 or
CC0 – 7
O–I
MOS
MEMORY SUPPORT ADDRESS BUS CONFIGURATION REGISTER C INPUT
MSA1–8 When RESET is inactive these pins drive the memory support address bus
CC0–7 When RESET is active Configuration Register C is loaded with the data value on
these pins If the user puts an external pull-up on any of these pins then the corresponding
register bit is set to a 1 If the pin is left unconnected then the register bit is 0
68 69
71 – 73
MSA9 – 13 or
DWID
EECONFIG
and SIG 5–7
O–I
MOS
MEMORY SUPPORT ADDRESS BUS DWID EECONFIG AND SIGNATURE REGISTER
MSA9–13 When RESET is inactive these pins drive the memory support address bus
DWID (MSA9) When RESET is active this input specifies whether the DP83907 is interfacing
to an 8-bit or 16-bit ISA bus If the user puts an external pull-up on this pin then the bus is
considered to be 16-bit If the pin is left unconnected then the bus is considered to be 8-bit
EECONFIG(MSA10) When RESET is active this input specifies whether the DP83907 loads
the configuration from an EEPROM or from the MSD0 – 15 and MSA1 – 8 pins If the user puts
an external pull-up on this pin then configuration data is loaded from the EEPROM If the pin
is left unconnected then configuration data is loaded from the memory support bus
SIG 5–7(MSA11–13) When RESET is active the most significant 3 bits of the signature
register are loaded with the data value on these pins If the user puts an external pull-up on
any of these pins then the corresponding register bit is set to a 1 If the pin is left
unconnected then the register bit is 0
76 MSRD
O
MOS
MEMORY SUPPORT BUS READ Strobes data from the external RAM into the DP83907 via
the memory support data bus
74 MSWR
O
MOS
MEMORY SUPPORT BUS WRITE Strobes data from the DP83907 into the external RAM
via the memory support data bus
Note Driver Types are I e Input O e Output I O e Bi-directional Output OCH e Open Collector 3ST e TRI-STATE Output TTL e TTL Compatible
AUI e Attachment Unit Interface TPI e Twisted Pair Interface LED e LED Drive MOS e CMOS Level Compatible XTAL e Crystal
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4 0 Functional Description (Continued)
The ISA standard determines that within 500 ns of RESET
going active all devices should enter the appropriate reset
condition The DP83907 will generate the internal signal
IOinactive after RESET has been active for 400 ns which
will disable all outputs and cause RESET to be the only
input monitored The DP83907 will not respond to a RESET
pulse of shorter duration than this An internal timer contin-
ues to monitor the amount of time RESET is active After
415 ms it is considered a valid Power-On-Reset and an in-
ternal signal called RegLoad is generated
When a Power-On-Reset occurs the DP83907 latches in the
values on the configuration pins and uses these to configure
the internal registers and options Internally these pins con-
tain pull-down resistors which are enabled when IOinactive
goes active If any pins are unconnected they default to a
logic zero The intemal pull-down resistor has a high resist-
ance to allow the external pull-up resistors to be of a high
value This limits the current taken by the memory support
bus The suggested external resistor value is 10 kX The
configuration registers are loaded from the memory support
bus when RESET goes inactive if RegLoad is active The
internal pull-down resistors are enabled onto the bus until
RegLoad has gone inactive
A Power-On-Reset also causes the DP83907 to load the
internal PROM space from the EEPROM which can take up
to 320 ms This occurs after RegLoad has gone inactive
The DP83907 will be inaccessible during this time If
EECONFIG is held high the configuration data loaded on
the falling edge of RESET will be overwritten with data read
from the serial EEPROM Regardless of the level on
EECONFIG the PROM space will always be loaded with
data from the serial EEPROM during the time specified
as EELoad
4 3 EEPROM OPERATION
The DP83907 uses an NMC93C06 or another serial
EEPROM with compatible timings The NMC93C06 is a 256-
bit device arranged as 16 words by 16 bits wide The pro-
grammed contents of the EEPROM is shown in Figure 7
D15 D0
0Fh EEPROM Code
Config C
0Eh Config B
Config A



08h 42h
42h
07h 57h
57h



03h Reserved
Reserved
02h E’net Address 5 E’net Address 4
01h E’net Address 3 E’net Address 2
00h E’net Address 1 E’net Address 0
FIGURE 7 EEPROM Programming Map
Mapping EEPROM into PROM Space
Data is read from the EEPROM at boot time and stored in
registers within the DP83907 While this operation takes
place the DP83907 can not be accessed by the system
These registers are mapped into the space traditionally oc-
cupied by the PROM in the NE2000
The user should program the EEPROM to contain the Ether-
net address in the first six bytes and whatever is required in
the next 8 bytes The user should then program 5757H and
4242H into address 07h and 08h respectively The
DP83907 device driver may determine that this is a 16-bit
board by checking this value
The DP83907 reads the first 8 words from the EEPROM and
maps them into the memory map at the appropriate ad-
dress
In Circuit ProgrammIng the EEPROM
If the upper byte of address 0Fh in the EEPROM does not
contain 073H then the DP83907 enters a mode that allows
the EEPROM contents to be programmed This can be used
in production to program the EEPROM in-situ By program-
ming 073H into the uppermost byte the EEPROM is protect-
ed from future adaptation except for configuration data
which can always be modified
If the EEPR bit of the Signature Register is low the
EEPROM program mode may be entered The EEPR bit is
low if the EEPROM code is not programmed as 73H In this
mode if the EELOAD bit of Configuration Register B is set
the user can directly control the EEPROM signals by writing
to the Data Transfer Port The user can write to the Data
Transfer Port and the value on the SD3 SD2 and SD1 pins
will be driven onto the EECS SK and DI outputs These
outputs will be latched The user can generate a clock on
SK by repetitively writing 1 then 0 to the appropriate bit This
can be used to generate the EEPROM signals as per the
NM93C06 data sheet
When the EEPROM has been programmed the user must
give the DP83907 a reset signal to return to normal opera-
tion and to read in the new data
Storing and Loading Configuration from EEPROM
If the EECONFIG function on MSA10 is high during boot up
the DP83907’s configuration is read from the EEPROM be-
fore the PROM data is read The configuration data is stored
within the upper two words of the EEPROM’s address
space Configuration Registers A and B are located in the
lower of these words Register C in the lower byte of the
upper word as shown in Figure 7
To write this configuration into the EEPROM the user must
follow the routine specified in the pseudo code below If the
EEPROM code byte in the EEPROM is programmed as 73H
the Configuration Registers may be written to in the
EPROM This operation will work regardless of the level on
EECONFIG The EELOAD bit of Configuration Register B
being set starts the EEPROM write process Care should be
taken not to accidentally set the GDLlNK bit and therefore
disable link integrity checking The next 3 writes to this reg-
ister load the values that will be stored in the configuration
register (note that the last 2 of these writes do not have to
follow the normal practice of preceding a write to this regis-
ter with a read to this address) The DP83907 will then com-
mence the EEPROM write The write has been completed
when the EELOAD bit goes to zero This loading proce-
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