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DP83902A Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DP83902A
Beschreibung ST-NICTM Serial Network Interface Controller for Twisted Pair
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 70 Seiten
DP83902A Datasheet, Funktion
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PRELIMINARY
November 1995
DP83902A ST-NICTM
Serial Network Interface Controller for Twisted Pair
General Description
The DP83902A Serial Network Interface Controller for
Twisted Pair (ST-NIC) is a microCMOS VLSI device de-
signed for easy implementation of CSMA CD local area net-
works These include Ethernet (10BASE5) Thin Ethernet
(10BASE2) and Twisted-pair Ethernet (10BASE-T) The
overall ST-NIC solution provides the Media Access Control
(MAC) and Encode-Decode (ENDEC) with an AUI interface
and 10BASE-T transceiver functions in accordance with the
IEEE 802 3 standards
The DP83902A’s 10BASE-T transceiver fully complies with
the IEEE standard This functional block incorporates the
receiver transmitter collision heartbeat loopback jabber
and link integrity blocks as defined in the standard The
transceiver when combined with equalization resistors
transmit receive filters and pulse transformers provides a
complete physical interface from the DP83902A’s ENDEC
module and the twisted pair medium
The integrated ENDEC module allows Manchester encod-
ing and decoding via a differential transceiver and phase
lock loop decoder at 10 Mbit sec Also included are colli-
sion detect translator and diagnostic loopback capability
The ENDEC module interfaces directly to the transceiver
module and also provides a fully IEEE compliant AUI (At-
tachment Unit Interface) for connection to other media
transceivers
(Continued)
Features
Y Single chip solution for IEEE 802 3 10BASE-T
Y Integrated controller ENDEC and transceiver
Y Full AUI interface
Y No external precision components required
Y 3 levels of loopback supported
Transceiver Module
Y Integrates transceiver electronics including
Transmitter and receiver
Collision detect heartbeat and jabber timer
Link integrity test
Y Link disable and polarity detection correction
Y Integrated smart receive squelch
Y Reduced squelch level for extended distance cable op-
eration (100-pin QFP version)
ENDEC Module
Y 10 Mb s Manchester encoding decoding plus clock re-
covery
Y Transmitter half or full step mode
Y Squelch on receive and collision pairs
Y Lock time 5 bits typical
Y Decodes Manchester data with up to g18 ns jitter
MAC Controller Module
Y 100% DP8390 software hardware compatible
Y Dual 16-bit DMA channels
Y 16-byte internal FIFO
Y Efficient buffer management implementation
Y Independent system and network clocks
Y Supports physical multicast and broadcast address fil-
tering
Y Network statistics storage
1 0 System Diagram
Station or DTE
TRI-STATE is a registered trademark of National Semiconductor Corporation
ST-NICTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11157
TL F 11157 – 1
RRD-B30M115 Printed in U S A
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DP83902A Datasheet, Funktion
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2 0 Pin Description (Continued)
PQFP PLCC AVJG
Pin No Pin No Pin No
Pin
Name
BUS INTERFACE PINS (Continued)
43 45 40 BACK
45 46 42 BREQ
52 53 50 RESET
NETWORK INTERFACE PINS
47 48 45 POL
49 50 47 TXE TX
50 51 48 COL
51 52 49 TEST
55 56
58 59
64 65
69
54 55
56 57
61 62
67
54 55
56 57
61 62
65
TXOdb
TXOa
TXOb
TXOda
RXIa
RXIb
GDLNK
LNKDIS
73 70 SQSEL
70 68 66 20 MHz
71 69 67 X1
72 70 69 GND
X2
74 71 71 SEL
I O Description
I BUS ACKNOWLEDGE Bus Acknowledge is an active high signal indicating that
the CPU has granted the bus to the DP83902A If immediate bus access is
desired BREQ should be tied to BACK Tying BACK to VCC will result in a
deadlock
O BUS REQUEST Bus Request is an active high signal used to request the bus for
DMA transfers This signal is automatically generated when the FIFO needs
servicing
I RESET Reset is active low and places the DP83902A in a reset mode
immediately No packets are transmitted or received by the DP83902A until STA
bit is set Affects Command Register Interrupt Mask Register Data Configuration
Register and Transmit Configuration Register The DP83902A will execute reset
within 10 BSCK cycles
O POLARITY A TTL MOS active high output This signal is normally in the low
state When the TPI module detects seven consecutive link pulses or three
consecutive received packets with reversed polarity POL is asserted
O TRANSMIT ENABLE TRANSMIT A TTL MOS active high output It is asserted
for approximately 50 ms whenever the DP83902A transmits data in either AUI or
TPI modes
O COLLISION A TTL MOS active high output It is asserted for approximately 50
ms whenever the DP83902A detects a collision in either the AUI or TPI modes
I FACTORY TEST INPUT Used to check the chip’s internal functions This should
be tied low during normal operation
O TWISTED PAIR TRANSMIT OUTPUTS These high drive CMOS level outputs
are resistively combined external to the chip to produce a differential output
signal with equalization to compensate for Intersymbol Interference (ISI) on the
twisted pair medium
I TWISTED PAIR RECEIVE INPUTS These inputs feed a differential amplifier
which passes valid data to the ENDEC module
I O GOOD LINK LINK DISABLE This pin has a dual function both input and output
The function is latched by the DP83902A on the rising edge of the Reset signal
i e on the chip returning to normal operation after reset
As an output this pin is configured as an open drain N-channel device and is
suitable for driving a LED It will be latched as output on removal of chip reset if
connected to a LED or left open circuit Under normal conditions (the twisted pair
link is not broken) the output will be low and the LED will be lit The open drain
output will be switched off if the twisted pair link has been detected to be broken
It is recommended that the color of the LED be green This output will be pulled
high in AUI mode by an internal resistor of approximately 15 kX
When this pin which has an internal pull-up resistor to VDD is tied low it becomes
an input and the link integrity checking is disabled
I TPI SQUELCH SELECT This pin selects the TPI module input squelch
thresholds When tied low the input squelch threshold on the RXIg inputs
complies to 10BASE-T specification When set high the RXIg input operates
with reduced squelch levels allowing its use with longer lengths of cable or cable
with higher losses If this pin is left unconnected an internal pulldown causes the
ST-NIC’s TPI to default to the higher squelch level
O 20 MHz This is a TTL MOS level signal It is a buffered version of the oscillator
X2 It is suitable to drive external logic
I EXTERNAL OSCILLATOR INPUT
I GROUND X2 If an oscillator is used this pin should be tied to ground and if a
crystal is used this pin should be tied directly to the crystal
I MODE SELECT When high TXa and TXb are the same voltage in the idle
state When low Transmita is positive with respect to Transmitb in the idle
state at the transformer’s primary
6
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4 0 Functional Description (Continued)
3 ST-NIC flushes remaining bytes from FIFO
4 ST-NIC performs internal processing to prepare for writ-
ing the header
5 ST-NIC writes 4-byte (2-word) header
6 ST-NIC de-asserts BREQ
FIFO Threshold Detection
To assure that no overwriting of data in the FIFO the FIFO
logic flags a FIFO overrun as the 13th byte is written into the
FIFO effectively shortening the FIFO to 13 bytes The FIFO
logic also operates differently in Byte Mode and in Word
Mode In Byte Mode a threshold is indicated when the na1
byte has entered the FIFO thus with an 8-byte threshold
the ST-NIC issues Bus Request (BREQ) when the 9th byte
has entered the FIFO For Word Mode BREQ is not gener-
ated until na2 bytes have entered the FIFO Thus with a
4 word threshold (equivalent to an 8-byte threshold) BREQ
is issued when the 10th byte has entered the FIFO
Beginning of Transmit
Before transmitting the ST-NIC performs a prefetch from
memory to load the FIFO The number of bytes prefetched
is the programmed FIFO threshold The next BREQ is not
issued until after the ST-NIC actually begins transmitting
data i e after SFD
Reading the FIFO
During normal operation the FIFO must not be read The
ST-NIC will not issue an ACKnowledge back to the CPU if
the FIFO is read The FIFO should only be read during loop-
back diagnostics
PROTOCOL PLA
The protocol PLA is responsible for implementing the IEEE
802 3 protocol including collision recovery with random
backoff The Protocol PLA also formats packets during
transmission and strips preamble and synch during recep-
tion
DMA AND BUFFER CONTROL LOGIC
The DMA and Buffer Control Logic is used to control two
16-bit DMA channels During reception the local DMA
stores packets in a receive buffer ring located in buffer
memory During transmission the Local DMA uses pro-
grammed pointer and length registers to transfer a packet
from local buffer memory to the FIFO A second DMA chan-
nel is used as a slave DMA to transfer data between the
local buffer memory and the host system The Local DMA
and Remote DMA are internally arbitrated with the Local
DMA channel having highest priority Both DMA channels
use a common external bus clock to generate all required
bus timing External arbitration is performed with a standard
bus request bus acknowledge handshake protocol
5 0 Transmit Receive Packet
Encapsulation Decapsulation
A standard IEEE 802 3 packet consists of the following
fields preamble Start of Frame Delimiter (SFD) destination
address source address length data and Frame Check
Sequence (FCS) The typical format is shown in Figure 2
The packets are Manchester encoded and decoded by the
ENDEC module and transferred serially to the NIC module
using NRZ data with a clock All fields are of fixed length
except for the data field The ST-NIC generates and ap-
pends the preamble SFD and FCS field during transmis-
sion The Preamble and SFD fields are stripped during re-
ception (The CRC is passed through to buffer memory dur-
ing reception )
PREAMBLE AND START OF FRAME DELIMITER (SFD)
The Manchester encoded alternating 1 0 preamble field is
used by the ENDEC to acquire bit synchronization with an
incoming packet When transmitted each packet contains
62 bits of alternating 1 0 preamble Some of this preamble
will be lost as the packet travels through the network The
preamble field is stripped by the NIC module Byte align-
ment is performed with the Start of Frame Delimiter (SFD)
pattern which consists of two consecutive 1’s The ST-NIC
does not treat the SFD pattern as a byte it detects only the
two bit pattern This allows any preceding preamble within
the SFD to be used for phase locking
DESTINATION ADDRESS
The destination address indicates the destination of the
packet on the network and is used to filter unwanted pack-
ets from reaching a node There are three types of address
formats supported by the ST-NIC physical multicast and
broadcast The physical address is a unique address that
corresponds only to a single node All physical addresses
have an MSB of ‘‘0’’ These addresses are compared to the
internally stored physical address registers Each bit in the
destination address must match in order for the ST-NIC to
accept the packet Multicast addresses begin with an MSB
of ‘‘1’’ The ST-NIC filters multicast addresses using a stan-
dard hashing algorithm that maps all multicast addresses
into a 6-bit value This 6-bit value indexes a 64-bit array that
filters the value If the address consists of all 1’s it is a
broadcast address indicating that the packet is intended for
all nodes A promiscuous mode allows reception of all pack-
ets the destination address is not required to match any
filters Physical broadcast multicast and promiscuous ad-
dress modes can be selected
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FIGURE 2
12
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