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PDF GE28F640L30 Data sheet ( Hoja de datos )
| Número de pieza | GE28F640L30 | |
| Descripción | Wireless Memory | |
| Fabricantes | Intel Corporation | |
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1.8 Volt Intel StrataFlash® Wireless
Memory with 3.0-Volt I/O (L30)
28F640L30, 28F128L30, 28F256L30
Datasheet
Product Features
■ High performance Read-While-Write/Erase
■ Software
— 90 ns initial access
— 20 µs (Typ) program suspend
— 50MHz with zero wait state, 17 ns clock-to-data
— 20 µs (Typ) erase suspend
output synchronous-burst mode
— Intel® Flash Data Integrator (FDI) optimized
— 25 ns asynchronous-page mode
— Basic Command Set (BCS) and Extended
— 4-, 8-, 16-, and continuous-word burst mode
Command Set (ECS) compatible
— Burst suspend
— Common Flash Interface (CFI) capable
— Programmable WAIT configuration
■ Security
— Buffered Enhanced Factory Programming
(Buffered EFP): 3.5 µs/byte (Typ)
— OTP space:
— 1.8 V low-power buffered and non-buffered
— 64 unique device identifier bits
programming @ 10 µs/byte (Typ)
— 64 user-programmable OTP bits
■ Architecture
— Asymmetrically-blocked architecture
— Multiple 8-Mbit partitions: 64Mb and 128Mb
devices
— Additional 2048 user-programmable OTP
bits
— Absolute write protection: VPP = GND
— Multiple 16-Mbit partitions: 256Mb devices
— Power-transition erase/program lockout
www.DataSheet4U.com— Four 16-KWord parameter blocks: top or
bottom configurations
— 64K-Word main blocks
— Individual zero-latency block locking
— Individual block lock-down
■ Quality and Reliability
— Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
— Expanded temperature: –25° C to +85° C
— Minimum 100,000 erase cycles per block
— Status register for partition and device status
— ETOX™ VIII process technology (0.13 µm)
■ Power
■ Density and Packaging
— 1.7 V - 2.0 V VCC operation
— I/O voltage: 2.2 V - 3.3 V
— 64-, 128- and 256-Mbit density in VF BGA
packages
— Standby current: 30 µA (Typ)
— 16-bit wide data bus
— 4-Word synchronous read current: 17 mA (Typ)
@ 54 MHz
— Automatic Power Savings (APS) mode
The 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O product is the latest generation of
Intel StrataFlash® memory devices featuring flexible, multiple-partition, dual operation. It provides high
performance synchronous-burst read mode and asynchronous read mode using 1.8 volt low-voltage, multi-
level cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one partition
while code execution or data reads take place in another partition. This dual-operation architecture also
allows two processors to interleave code operations while program and erase operations take place in the
background.
The 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O device is manufactured using Intel
0.13 µm ETOX™ VIII process technology. It is available in industry-standard chip scale packaging.
.
Notice: This document contains information on products in the design phase of
development. The information here is subject to change without notice. Do not finalize
a design with this information.
Order Number: 251903-002
February 2003
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28F640L30, 28F128L30, 28F256L30
12.0
AC Characteristics...................................................................................................52
12.1
12.2
12.3
12.4
12.5
12.6
AC Read Specifications (VCCQ = 2.2 V – 3.3 V) ................................................52
AC Write Specifications.......................................................................................57
Program and Erase Characteristics ....................................................................61
Reset Specifications............................................................................................61
AC Test Conditions .............................................................................................62
Capacitance ........................................................................................................63
Appendix A Write State Machine (WSM) ............................................................................64
Appendix B Flowcharts .............................................................................................................71
Appendix C Common Flash Interface..................................................................................80
Appendix D Mechanical Information....................................................................................90
Appendix E Additional Information ......................................................................................92
Appendix F Ordering Information.........................................................................................93
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28F640L30, 28F128L30, 28F256L30
2.3 Signal Descriptions
Table 1 describes the active signals used on the L30 flash memory device.
Table 1. Signal Descriptions
Symbol
Type
Name and Function
A[MAX:0]
D[15:0]
ADV#
CE#
CLK
OE#
RST#
WAIT
WE#
WP#
VPP
VCC
VCCQ
VSS
VSSQ
DU
NC
RFU
In
In/Out
In
In
In
In
In
Out
In
In
Pwr
Pwr
Pwr
Pwr
Pwr
-
-
-
ADDRESS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0].
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during memory,
Status Register, Protection Register, and Read Configuration Register reads. Data balls float when the
CE# or OE# are de-asserted. Data is internally latched during writes.
ADDRESS VALID: Active-low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through if
ADV# is held low.
CHIP ENABLE: Active-low input. CE#-low selects the device. CE#-high deselects the device, placing it
in standby, with D[15:0] and WAIT in High-Z.
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode and
increments the internal address generator. During synchronous read operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs
first.
OUTPUT ENABLE: Active-low input. OE#-low enables the device’s output data buffers during read
cycles. OE#-high places the data outputs in High-Z and WAIT in High-Z.
RESET: Active-low input. RST# resets internal automation and inhibits write operations. This provides
data protection during power transitions. RST#-high enables normal operation. Exit from reset places
www.DataSheet4U.comthe device in asynchronous read array mode.
WAIT: Indicates data valid in synchronous array or non-array burst reads. Configuration Register bit 10
(CR.10, WT) determines its polarity when asserted. With CE# and OE# at VIL, WAIT’s active output is
VOL or VOH when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when de-asserted.
• In asynchronous page mode, and all write modes, WAIT is de-asserted.
WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on
the rising edge of WE#.
WRITE PROTECT: Active-low input. WP#-low enables the lock-down mechanism. Blocks in lock-down
cannot be unlocked with the Unlock command. WP#-high overrides the lock-down function enabling
blocks to be erased or programmed using software commands.
ERASE/ PROGRAM POWER: Valid VPP voltages on this ball allow block erase and program functions.
Flash memory array contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid
VPP voltages should not be attempted.
DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
OUTPUT POWER SUPPLY: Output-driver source voltage.
GROUND: Ground reference for device logic voltages. Connect to system ground.
GROUND: Ground reference for device output voltages. Connect to system ground.
DON’T USE: Do not use this ball. This ball should not be connected to any power supplies, signals or
other balls, and must be left floating.
NO CONNECT: No internal connection; can be driven or floated.
RESERVED for FUTURE USE: Reserved by Intel for future device functionality and enhancement.
Datasheet
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