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AD9889 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9889
Beschreibung High Performance HDMI/DVI Transmitter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9889 Datasheet, Funktion
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High Performance
HDMI™/DVI Transmitter
AD9889
FEATURES
FUNCTIONAL BLOCK DIAGRAM
HDMI/DVI transmitter compatible with HDMI 1.1 and
HDCP 1.1
Single 1.8 V power supply
Video/audio inputs are 3.3 V tolerant
80-lead, Pb-free LQFP
Digital video
80 MHz operation supports all video formats from 480i to
1080i and 720p
Programmable 2-way color space converter
Supports RGB, YCbCr, DDR, ITU656 formats
Auto input video format detection
Digital audio
Supports standard S/PDIF for stereo or compressed audio
up to 192 kHz
8-channel LPCM I2S audio up to 192 kHz
HTPG
SCL SDA MCL MDA
REGISTER
CONFIGURATION
LOGIC
I2C
SLAVE
I2C
MASTER
HDCP
CONTROLLER
DDSDA
DDCSCL
CLK
VSYNC
HSYNC
DE
D[23:0]
VIDEO
DATA
CAPTURE
HDCP
CIPHER
COLOR
SPACE
CONVERSION
4:2:2
TO
4:4:4
CONVERSION
XOR
MASK
HDM
ITX
CORE
SWING_ADJ
Tx0[1:0]
Tx1[1:0]
Tx2[1:0]
TxC[1:0]
Special features for easy system design
On-chip MPU to perform HDCP operations
On-chip I2C master to handle EDID reading
5 V tolerant I2C and MPD I/Os, no extra device needed
S/PDIF
MCLK
I2S[3:0]
AUDIO
DATA
CAPTURE
Figure 1.
No audio master clock needed for S/PDIF support
www.DataSheet4U.comAPPLICATIONS
AD9889
05675-001
DVD players and recorders
Digital set-top boxes
AV receivers
Digital cameras and camcorders
GENERAL DESCRIPTION
The AD9889 is an 80 MHz, high-definition multimedia inter-
face (HDMITM 1.1) transmitter. It supports HDTV formats up
to 1080i and 720p, and graphic resolutions up to XGA (1024 ×
768 @ 75 Hz). With the inclusion of HDCP, the AD9889 allows
the secure transmission of protected content as specified by the
HDCP 1.1 protocol.
The AD9889 supports both S/PDIF and 8-channel I2S audio.
Its high fidelity 8-channel I2S can transmit either stereo or
7.1 surround audio at 192 kHz. The S/PDIF can carry stereo
LPCM (linear pulse code modulation) audio or compressed
audio including Dolby® Digital, DTS®, and THX®.
The AD9889 helps to reduce system design complexity and cost
by incorporating such features as HDCP master, I2C master for
EDID reading, a single 1.8 V power supply, and 5 V tolerance
on I2C and hot plug detect pins.
Fabricated in an advanced CMOS process, the AD9889 is pro-
vided in a space-saving, 80-lead, surface-mount, Pb-free plastic
LQFP and is specified over the 0°C to 70°C temperature range.
EVALUATION KITS AND OTHER RESOURCES
Evaluation kits, reference design schematics, software quick
start guide, and codes are available from Analog Devices local
sales and marketing personnel.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
DataSheet4 U .com
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
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AD9889 Datasheet, Funktion
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AD9889
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVDD 1
D0 2
DE 3
HSYNC 4
VSYNC 5
CLK 6
S/PDIF 7
MCLK 8
I2S0 9
I2S1 10
I2S2 11
I2S3 12
SCLK 13
LRCLK 14
GND 15
PVDD 16
GND 17
GND 18
PVDD 19
PVDD 20
PIN 1
AD9889
TOP VIEW
(Not to Scale)
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60 GND
59 GND
58 D15
57 D16
56 D17
55 D18
54 D19
53 D20
52 D21
51 D22
50 D23
49 MCL
48 MDA
47 SDA
46 SCL
45 DDSDA
44 DDCSCL
43 GND
42 GND
41 AVDD
Table 4. Complete Pinout List
Pin Type
Pin No.
INPUTS
50 to 58,
65 to 78, 2
6
3
4
5
23
25
7
8
12 to 9
13
14
33
OUTPUTS
28, 27
38, 37
35, 34
31, 30
40
www.DataSheet4U.comFigure 2. Pin Configuration
Mnemonic Description
D[23:0]
CLK
DE
HSYNC
VSYNC
EXT_SW
HPD
S/PDIF
MCLK
I2S[3:0]
SCLK
LRCLK
PD/A0
TxC+
TxC−
Tx2+
Tx2−
Tx1+
Tx1−
Tx0+
Tx0−
INT
Video Data Input
Video Clock Input
Data Enable Bit for Digital Video
Horizontal SYNC Input
Vertical SYNC Input
Differential Output Swing Adjustment
Hot Plug Detect Signal
S/PDIF (Sony/Philips Digital Interface) Audio Input Pin
Audio Reference Clock, 128 × fs or 256 × fs
I2S Audio Data Inputs
I2S Audio Clock
Left/Right Channel Selection
Power-Down Control
Differential Clock Output
Differential Clock Output Complement
Differential Output Channel 2
Differential Output Channel 2 Complement
Differential Output Channel 1
Differential Output Channel 1 Complement
Differential Output Channel 0
Differential Output Channel 0 Complement
Monitor Sense Connection Status
Rev. 0 | Page 6 of 48
D a t a 4SU .h ce oe mt
Value
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
TMDS
TMDS
TMDS
TMDS
1.8 V CMOS
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AD9889 pdf, datenblatt
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AD9889
YCbCr 4:2:2 DDR (Double Data Rate) Formats (12 Bits, 10 Bits, or 8 Bits) with Embedded Syncs. Input ID = 4
An input with YCbCr 4:2:2 DDR data and embedded syncs (ITU 656) can be selected by setting the input ID (R0x15[3:1]) to 0b100. The
input CS (R0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with R0x16[5:4]. The two input pin
assignment styles are shown in Table 14. The input style can be set in R0x16[3:2]. The order of data input is the order in the table (for
example, 12-bit data is accepted as Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3).
Table 14.
Data <23:0>
Input Format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Style 1
12-bit
Cb/Y/Cr/Y[11:4]
[3:0]
10-bit
Cb/Y/Cr/Y[9:2]
[1:0]
8-bit Cb/Y/Cr/Y[7:0]
Style 2
12-bit
Cb/Y/Cr/Y[11:0]
10-bit
Cb/Y/Cr/Y[9:0]
8-bit Cb/Y/Cr/Y[7:0]
Normal 4:4:4 input format (RGB or YCbCr) Clocked at Double Data Rate (DDR), Input ID = 5
An input with YCbCr 4:2:2 DDR data and separate syncs can be selected by setting the input ID (R0x15[3:1]) to 0b011. The input CS
(R0x16[0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with R0x16[5:4]. The three input pin assignment
styles are shown in Table 15. The input style can be set in R0x16[3:2].
Table 15.
Input Format
RGB 4:4:4 (DDR)
(1 st edge,
2 nd edge)
YCbCr 4:4:4 (DDR)
(1 st edge,
2 nd edge)
RGB 4:4:4 (DDR)
(1 st edge,
2 nd edge)
YCbCr 4:4:4 (DDR)
(1 st edge,
2 nd edge)
YCbCr 4:4:4 (DDR)
(1 st edge,
2 nd edge)
Data <23:0>
www.DataSheet4U.com23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Style 1
G[3:0]
B[7:0]
R[7:0]
G[7:4]
Style 2
Y[3:0]
Cr[7:0]
R[7:0]
G[3:0]
Cb[7:0]
B[7:0]
Y[7:4]
G[7:4]
Cr[7:0]
Y[7:4]
Style 3
Y[3:0]
Y[7:0]
Cb[3:0]
Cb[7:0]
Cr[7:0]
Cb[7:4]
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Rev. 0 | Page 12 of 48
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