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PDF DS1868 Data sheet ( Hoja de datos )
| Número de pieza | DS1868 | |
| Descripción | Dual Digital Potentiometer Chip | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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DS1868
Dual Digital Potentiometer Chip
FEATURES
PIN ASSIGNMENT
§ Ultra-lowpower consumption, quiet, pumpless
design
§ Two digitally controlled, 256-position
potentiometers
§ Serial port provides means for setting and
reading both potentiometers
§ Resistors can be connected in series to
provide increased total resistance
§ 20-pin TSSOP, 16-pin SOIC, and 14-pin DIP
VB
DNC
H1
L1
W1
RST
CLK
DNC
DNC
1
2
3
4
5
6
7
8
9
20 VCC
19 DNC
18 DNC
17 SOUT
16 W0
15 H0
14 L0
13 COUT
12 DNC
packages are available.
GND
10
11 DQ VB 1
§ Resistive elements are temperature
20-Pin TSSOP (173-mil)
H1 2
compensated to ±0.3 LSB relative linearity
§ Standard resistance values:
- DS1868-10 ∼ 10 kΩ
VB 1 16 VCC L1 3
NC 2 15 NC
H1 3 14 SOUT W1 4
- DS1868-50 ∼ 50 kΩ
- DS1868-100 ∼ 100 kΩ
www.DataSheet4U.com§ +5V or ±3V operation
L1 4 13 W0 RST 5
W1 5 12 H0
RST 6 11 L0 CLK 6
CLK 7 10 COUT
§ Operating Temperature Range:
GND
8
9 DQ GND 7
14
13
12
11
10
9
8
- Industrial: -40°C to 85°C
DS1868S 16-Pin SOIC (300-mil)
14-Pin DIP (300-mil)
VCC
SOUT
W0
H0
L0
COUT
DQ
PIN DESCRIPTION
L0, L1
- Low End of Resistor
H0, H1
- High End of Resistor
W0, W1
- Wiper Terminal of Resistor
SOUT
- Stacked Configuration Output
RST - Serial Port Reset Input
DQ - Serial Port Data Input
CLK
- Serial Port Clock Input
COUT
VCC
GND
- Cascade Port Output
- +5 Volt Supply
- Ground Connections
NC - No Internal Connection
VB
DNC
- Substrate Bias Voltage
- Do Not Connect
*All GND pins must be connected to ground.
DESCRIPTION
The DS1868 Dual Digital Potentiometer Chip consists of two digitally controlled solid-state
potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section
and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the
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STACKED CONFIGURATION Figure 3
DS1868
CASCADE OPERATION
A feature of the DS1868 is the ability to control multiple devices from a single processor. Multiple
DS1868s can be linked or daisy chained as shown in Figure 4. As a data bit is entered into the I/O shift
register of the DS1868 a bit will appear at the COUT output after a minimum delay of 50 nanoseconds. The
stack select bit of the DS1868 will always be the first out the part at the beginning of a transaction. The
COUT pin will always have the value of the stack select bit (b0) when RST is inactive.
CASCADING MULTIPLE DEVICES Figure 4
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The COUT output of the DS1868 can be used to drive the DQ input of another DS1868. When connecting
multiple devices, the total number of bits transmitted is always 17 times the number of DS1868s in the
daisy chain.
An optional feedback resistor can be placed between the COUT terminal of the last device and the first
DS1868 DQ, input thus allowing the controlling processor to read, as well as, write data, or circularly
clock data through the daisy chain. The value of the feedback or isolation resistor should be in the range
from 2 to 10 kohms.
When reading data via the COUT pin and isolation resistor, the DQ line is left floating by the reading
device. When RST is driven high, bit 17 is present on the COUT pin, which is fed back to the input DQ
pin through the isolation resistor. When the CLK input transitions low to high, bit 17 is loaded into the
first position of the I/O shift register and bit 16 becomes present on COUT and DQ of the next device. After
17 bits (or 17 times the number of DS1868s in the daisy chain), the data has shifted completely around
and back to its original position. When RST transitions to the low state to end data transfer, the value (the
same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit I/O register.
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CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
CIN
COUT
MIN
TYP
MAX
5
7
DS1868
(tA=25°C)
UNITS NOTES
pF 3, 6
pF 3, 6
AC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C; VCC=5.0V ±10%)
PARAMETER
SYMBOL MIN TYP MAX UNITS NOTES
CLK Frequency
fCLK
DC
10 MHz
10
Width of CLK Pulse
tCH 50
ns 10
Data Setup Time
tDC 30
ns 10
Data Hold Time
tCDH
10
ns 10
Propagation Delay Time Low to High Level
Clock to Output
tPLH
50 ns 10, 13
Propagation Delay Time High to Low Level
tPLH
50 ns 10, 13
RST High to Clock Input High
tCC 50
ns 10
RST Low from Clock Input High
tHLT 50
ns 10
RST Inactive
tRLT 125
ns 10
Clock Low to Data Valid on a Read
tCDD
30 ns
10
www.DataSheet4U.comCLK Rise Time, CLK Fall Time
tCR
50 ns
10
NOTES:
1. All voltages are referenced to ground.
2. Resistor inputs cannot exceed VB - 0.5V in the negative direction.
3. Capacitance values apply at 25°C.
4. Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper
position. Device test limits ±1.6 LSB.
5. Relative linearity is used to determine the change in voltage between successive tap positions. Device
test limits ±0.5 LSB.
6. Typical values are for tA = 25°C and nominal supply voltage.
7. -3 dB cutoff frequency characteristics for the DS1868 depend on potentiometer total resistance:
DS1868-010; 1 MHz, DS1868-050; 200 kHz; and DS1868-100; 80 kHz.
8. Cout is active regardless of the state of RST .
9. VREF = 1.5 volts.
10. See Figure 9(a), (b), and (c).
11. Noise < -120 dB/ Hz . Reference 1 volt (thermal).
12. Supply current is dependent on clock rate (see Figure 11).
13. See Figure 10.
14. Standby currents apply when RST , LLIC, DQ are in the low-state.
15. When biasing the substrate minimum VB = -3.0V ±10% and maximum VCC = 3.0V ±10%.
16. Valid at 25°C only.
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