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PDF DRX3960A Data sheet ( Hoja de datos )
| Número de pieza | DRX3960A | |
| Descripción | Digital Receiver Front-end | |
| Fabricantes | Micronas | |
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ADVANCE INFORMATION
DRX 3960A
Digital Receiver
Front-end
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Edition Feb. 8, 2001
6251-510-2AI
MICRONAS
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1 page  
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ADVANCE INFORMATION
DRX 3960A
1.2. Quick Reference Data
Parameter
Min.
Typ.
Max. Unit
Remarks
Supply voltage, analog
5V
Current consumption, analog
110 mA
Supply voltage, digital
3.3 V
Current consumption, digital
60 mA
Input frequency
30 47 MHz
Maximum wanted signal input voltage
minimum TOP gain:
maximum TOP gain:
Lock in range
200
20
0.8
1.0
mVpp
mVpp
MHz
MHz
direction adjacent channel
direction own channel
center freq. quartz stable
Intermodulation ratio α1.07
65 dB blue picture, PSC1=−13dB,
no sound shelf
Weighted video S/N (CCIR567, 10 kHz...5 MHz)
56 58
dB
Unweighted video S/N (10 kHz...5 MHz)
49 51
dB
Weighted sound S/N (black, CCIR468 quasi peak, SC1/SC2)
62/58
dB dev. = 27 kHz
Weighted sound S/N (FuBK, CCIR468 quasi peak, SC1/SC2)
55/50
dB dev. = 27 kHz
www.DataSheet4U.comCVBS output voltage
2 Vpp programmable
Second IF output voltage
0.8 Vpp programmable
Delayed Tuner AGC external voltage
8V
Micronas
5
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ADVANCE INFORMATION
DRX 3960A
4. Control Interface
4.1. I2C Bus Interface
4.1.1. Device and Subaddresses
The DRX 3960A is controlled via the I2C bus slave
interface.
The IC is selected by transmitting one of the
DRX 3960A device addresses. In order to allow up to
three ICs to be connected to a single bus, an address
select pin (ADR_SEL) has been implemented. With
ADR_SEL pulled to high, low, or left open, the
DRX 3960A responds to different device addresses. A
device address pair is defined as a write address and a
read address.
Writing is done by sending the device write address,
followed by the subaddress byte, two address bytes,
and two data bytes. Reading is done by sending the
write device address, followed by the subaddress byte
and two address bytes. Without sending a stop condi-
tion, reading of the addressed data is completed by
sending the device read address and reading two
bytes of data.
Due to the internal architecture of the DRX 3960A, the
IC cannot react immediately to an I2C request. The
typical response time is about 0.3 ms. If the
www.DataSheet4U.comDRX 3960A cannot accept another complete byte of
data until it has performed some other function (for
example, servicing an internal interrupt), it will hold the
clock line low to force the transmitter into a wait state.
The maximum wait period during normal operation
mode is less than 1 ms.
Table 4–1: I2C Bus Device Addresses
ADR_SEL
Mode
Device address
Write
82hex
Low
Read
83hex
Write
86hex
High
Read
87hex
Left Open
Write
Read
8Ahex
8Bhex
Table 4–2: I2C Bus Subaddresses
Name
CONTROL
Binary Value
0000 0000
Hex Value
00
PORT
WR_DRX
RD_DRX
0000 0011
0001 0000
0001 0001
03
10
11
Mode
Read/Write
Write
Write
Write
Function
Write
Read
: Software reset of DRX
: Hardware error status of DRX
output port address
write address
read address
Micronas
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